PRODUCT DATASHEET
AAT2860
TM
ChargePump
Backlight/Flash LED Driver and Multiple LDO Lighting Management Unit
Capacitor Selection
PCB Layout
Careful selection of the eight external capacitors CIN, C1,
C2, CLDO(A/B/C), and COUT are important because they will
affect turn on time, output ripple and transient perfor-
mance. Optimum performance will be obtained when low
ESR (<100mΩ) ceramic capacitors are used. In general,
low ESR is defined as a resistance that is less than
100mΩ.
To achieve adequate electrical and thermal performance,
careful attention must be given to the PCB layout. In the
worst-case operating condition, the chip must dissipate
considerable power at full load. Adequate heat-sinking
must be achieved to ensure intended operation.
Figures 6 and 7 illustrate an example PCB layout. The
bottom of the package features an exposed metal pad.
The exposed pad acts, thermally, to transfer heat from
the chip and, electrically, as a ground connection.
X7R and X5R type ceramic capacitors are highly recom-
mended over all other types of capacitors for use with
the AAT2860. For the charge pump section, a 1µF or
greater capacitor is required for the fly (C1 and C2)
capacitors. The three LDOs require a 2.2µF or greater
output capacitor. The required input capacitor (CIN) is
The junction-to-ambient thermal resistance (θJA) for the
connection can be significantly reduced by following a
couple of important PCB design guidelines. The PCB area
directly underneath the package should be plated so that
the exposed paddle can be mated to the top layer PCB
copper during the reflow process. Multiple copper plated
thru-holes should be used to electrically and thermally
connect the top surface pad area to additional ground
plane(s).
4.7μF or greater and the required output capacitor (COUT
)
is 2.2μF or greater.
Ceramic capacitors offer many advantages over their
tantalum and aluminum electrolytic counterparts. A
ceramic capacitor typically has very low ESR, is lowest
cost, has a smaller printed circuit board (PCB) footprint,
and is non-polarized. Low ESR ceramic capacitors maxi-
mize charge pump transient response.
The chip ground is internally connected to both the
exposed pad and to the AGND and PGND pins. It is good
practice to connect the GND pins to the exposed pad
area with traces.
Before choosing a particular capacitor, verify the capaci-
tor’s performance with the characteristics illustrated in
the component’s data sheet. Performance verification
will help avoid undesirable component related perfor-
mance deficiencies. Suggested typical ceramic capacitor
components for the AAT2860 are listed in Table 11.
The flying capacitors (C1 and C2), input capacitors (C3
and C4), and output capacitor (C5, C6, C7, and C8)
should be connected as close as possible to the IC. In
addition to the external passive components being
placed as close as possible to the IC, all traces connect-
ing the AAT2860 should be as short and wide as possible
to minimize path resistance and potential coupling.
Manufacturer
Part Number
Value
Voltage
Temp. Co.
Case
0603ZD105K
0603ZD225K
1μF
2.2μF
1μF
2.2μF
4.7μF
1μF
10
10
25
16
10
16
10
10
AVX
X5R
0603
C1608X5R1E105K
C1608X5R1C225K
C1608X5R1A475K
GRM188R61C105K
GRM188R61A225K
LMK107BJ475KA
TDK
X5R
0603
Murata
X5R
X5R
0603
0603
2.2μF
4.7μF
Taiyo Yuden
Table 11: Surface Mount Capacitors.
w w w . a n a l o g i c t e c h . c o m
2860.2008.05.1.0
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