PRODUCT DATASHEET
AAT2789
SystemPowerTM
Low Noise, High Frequency Dual Step-Down Converter
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2789. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple. The
proper placement of the input capacitor (C1) can be
seen in the evaluation board layout in the Layout section
of this datasheet (see Figures 1 and 2).
3 · ΔILOAD
=
COUT
VDROOP · FS
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 10ꢀF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result. Since the inductance of a
short PCB trace feeding the input voltage is significantly
lower than the power leads from the bench power sup-
ply, most applications do not exhibit this problem.
The maximum output capacitor RMS ripple current is
given by:
V
OUT · (VIN(MAX) - VOUT)
1
IRMS(MAX)
=
·
L · FS · VIN(MAX)
2· 3
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR/ESL bypass ceramic capacitor. This dampens
the high Q network and stabilizes the system.
Channel 2
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7ꢀF to
10ꢀF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
Output Capacitor
Channel 1
Output Voltage
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10ꢀF to
22ꢀF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
The AAT2789 output voltages are programmed with
external resistors R1, R2 (Channel 1) and R3, R4 (Channel
2). To limit the bias current required for the external feed-
back resistor string while maintaining good noise immu-
nity, the minimum suggested value for R2 and R4 are
59kΩ. Although a larger value will further reduce quies-
cent current, it will also increase the impedance of the
feedback node, making it more sensitive to external noise
and interference. Table 1 summarizes the resistor values
for various output voltages with R2 and R4 set to either
59kΩ for good noise immunity or 221kΩ for reduced no
load input current.
The output voltage droop due to a load transient is
dominated by the capacitance of the ceramic output
capacitor. During a step increase in load current, the
ceramic output capacitor alone supplies the load current
until the loop responds. Within two or three switching
cycles, the loop responds and the inductor current
increases to match the load current demand. The rela-
tionship of the output voltage droop during the three
switching cycles to the output capacitance can be esti-
mated by:
w w w . a n a l o g i c t e c h . c o m
2789.2008.03.1.0
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