PRODUCT DATASHEET
AAT2784
SystemPowerTM
3-Channel Step-Down DC/DC Converter
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 6.3V, X5R
ceramic capacitor with 5.0V DC applied is actually about
6μF. The maximum input capacitor RMS current is:
0.75 VO
m
0.75 1.2V
A
0.75
µs
L =
=
= 1.2µH
The inductor should be set equal to the output voltage
numeric value in micro henries (μH). This guarantees
that there is sufficient internal slope compensation.
Manufacturer’s specifications list both the inductor DC
current rating, which is a thermal limitation, and the
peak current rating, which is determined by the satura-
tion characteristics. The inductor should not show any
appreciable saturation under normal load conditions.
Some inductors may meet the peak and average current
ratings yet result in excessive losses due to a high DCR.
Always consider the losses associated with the DCR and
its effect on the total converter efficiency when selecting
an inductor. For channel 3, the 1.5μH LQH32PN1R5NN0L
series Murata inductor has a 68.4mΩ worst case DCR
and a 1.75A DC current rating. At full 1.5A load, the
inductor DC loss is 154mW which gives less than 5%
loss in efficiency for a 1.5A, 1.2V output.
VO
VIN
VO
VIN
IRMS = IO ·
· 1 -
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
VO
VIN
VO
VIN
1
2
· 1 -
=
D · (1 - D) = 0.52 =
for VIN = 2 · VO
IO
IRMS(MAX)
=
2
Input Capacitor
The term appears in both the input voltage ripple and
input capacitor RMS current equations and is a maxi-
mum when VO is twice VIN. This is why the input voltage
ripple and the input capacitor RMS current ripple are a
maximum at 50% duty cycle. The input capacitor pro-
vides a low impedance loop for the edges of pulsed cur-
rent drawn by the AAT2784. Low ESR/ESL X7R and X5R
ceramic capacitors are ideal for this function. To mini-
mize stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high fre-
quency content of the input current localized, minimizing
EMI and input voltage ripple. The proper placement of
the input capacitor (C1) can be seen in the evaluation
board layout in the Layout section of this datasheet (see
Figure 2). A laboratory test set-up typically consists of
two long wires running from the bench power supply to
the evaluation board input voltage pins. The inductance
of these wires, along with the low-ESR ceramic input
capacitor, can create a high Q network that may affect
converter performance. This problem often becomes
apparent in the form of excessive ringing in the output
voltage during load transients. Errors in the loop phase
and gain measurements can also result. Since the induc-
tance of a short PCB trace feeding the input voltage is
significantly lower than the power leads from the bench
power supply, most applications do not exhibit this prob-
lem. In applications where the input power source lead
inductance cannot be reduced to a level that does not
Select a 10μF to 22μF X7R or X5R ceramic capacitor for
the VP1_2 and VP3 inputs. To estimate the required
input capacitor size, determine the acceptable input
ripple level (VPP) and solve for CIN. The calculated value
varies with input voltage and is a maximum when VIN is
double the output voltage.
Output
Slope
Configuration Voltage Inductor Compensation
0.6V-
2.2μH
0.6V adjustable
with external
resistive divider
2.0V
2.5V
3.3V
0.6A/μs
3.3μH
4.7μH
Table 1: AAT2784 Inductor Values.
VO
VIN
VO
VIN
· 1 -
CIN =
VPP
IO
- ESR ·FS
VO
VIN
VO
VIN
1
· 1 -
=
for VIN = 2 · VO
4
1
CIN(MIN)
=
VPP
IO
- ESR · 4 · FS
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2784.2007.11.1.1
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