PRODUCT DATASHEET
AAT2689
TM
SystemPower PMIC Solution for 12V Adapter Systems with 2-Output High Performance Step-Down Converters
For asynchronous step-down converter operation, the
power dissipation is only in the internal high side MOSFET
during the on time. When the switch is off, the power
dissipates on the external Schottky diode. Total package
loss for AAT2689 reduces to the following equation:
2. C1, L1, D2, C9 and C11 should be placed as close as
possible to minimize any parasitic inductance in the
switched current path which generates a large volt-
age spike during the switching interval. The connec-
tion of inductor to switching node should be as short
as possible.
3. The feedback trace or FB1 pin should be separated
from any power trace and connected as close as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
PTOTAL = IOUT12 · RDS(ON)H · D + (tSW · FS · IOUT1 + IQ1) · VIN1 + (VIN2 - VOUT2) · IOUT2
VOUT
where D =
is the duty cycle.
VIN
4. The resistance of the trace from the load returns to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
Since RDS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θJA for the TDFN34-16
package, which is 50°C/W.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
6. The critical small signal components include feed-
back components, and compensation components
should be placed close to the FB1 and COMP1 pins.
The feedback resistors should be located as close as
possible to the FB1 pin with its ground tied straight
to the signal ground plane which is separated from
power ground plane.
7. C7 should be connected close to the RS1 and OS1
pins, while R2 should be connected directly to the
output pin of the inductor. For the best current limit
performance, C7 and R2 should be placed on the bot-
tom layer to avoid noise coupling from the inductor.
8. For good thermal coupling, PCB vias are required
from exposed pad 1 (EP1) to the bottom ground
plane and from exposed pad 2 (EP2) to the bottom
VIN plane.
TJ(MAX) = PTOTAL · θJA + TAMB
Layout Considerations
The suggested PCB layout for the AAT2689 is shown in
Figures 4, 5, and 6. The following guidelines should be
used to help ensure a proper layout.
1. The power input capacitors (C1 and C15) should be
connected as close as possible to high voltage input
pin (IN1) and power ground.
w w w . a n a l o g i c t e c h . c o m
2689.2008.06.1.0
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