PRODUCT DATASHEET
AAT2603
Total Power Solution for Portable Applications
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
EP
Symbol
LX2
ENB2
FBB2
ENL3
AGND
FBL3
OUTL3
INL34
OUTL4
FBL4
ENL4
BYP
ENL1
FBL1
OUTL1
INL12
OUTL2
FBL2
ENL2
AIN
FBB1
ENB1
SELB2
LX1
PGND1
INB1
INB2
PGND2
Function
DC-DC2 (Buck2) switching node. Connect the output inductor to LX2. Connected internally to the
drains o f both high-side and low-side switches.
DC-DC2 (Buck2) enable input. Active high.
DC-DC2 (Buck2) feedback input. For externally adjustable versions, connect a resistor divider
from Buck2 output to FBB2 to AGND to set the Buck2 output voltage.
LDO3 enable input. Active high.
Analog ground. Connect AGND to PGND1 and PGND2 as close as possible to the device.
LDO3 feedback input. Connect a resistor divider from OUTL3 to FBL3 to AGND to set the LDO3
output voltage.
LDO3 output. Should be closely decoupled to AGND with a 4.7μF or greater capacitor.
LDO3 and LDO4 input. Should be closely decoupled to AGND with a 2.2μF or greater capacitor.
LDO4 output. Should be closely decoupled to AGND with a 4.7μF or greater capacitor.
LDO4 feedback input. Connect a resistor divider from OUTL4 to FBL4 to AGND to set the LDO4
output voltage.
LDO4 enable input. Active high.
Reference Bypass. Bypass BYP to AGND with a 0.01μF or greater capacitor to reduce the LDO1
output noise.
LDO1 enable input. Active high.
LDO1 feedback input. Connect a resistor divider from OUTL1 to FBL1 to AGND to set the LDO1
output voltage.
LDO1 output. Should be closely decoupled to AGND with a 4.7μF or greater capacitor.
LDO1 and LDO2 input. Should be closely decoupled to AGND with a 2.2μF or greater capacitor.
LDO2 output. Should be closely decoupled to AGND with a 4.7μF or greater capacitor.
LDO2 feedback input. Connect a resistor divider from OUTL2 to FBL2 to AGND to set the LDO2
output voltage.
LDO2 enable input. Active high.
Analog voltage input. AIN is the bias supply for the device. Should be closely decoupled to AGND
with a 2.2μF or greater capacitor.
DC-DC1 (Buck1) feedback input. For externally adjustable versions, connect a resistor divider
from Buck1 output to FBB1 to AGND to set the Buck1 output voltage.
DC-DC1 (Buck1) enable input. Active high.
Dynamically adjusts the output voltage of DC-DC2 (Buck2) (Logic High=1.3V, Logic Low=1.0V)
DC-DC1 (Buck1) switching node. Connect the output inductor to LX1. Connected internally to the
drains of both high-side and low-side switches.
DC-DC1 (Buck1) power ground. Connected internally to the source of the Buck1 N-channel syn-
chronous rectifier. Connect PGND1 to PGND2 and AGND as close as possible to the device.
DC-DC1 (Buck1) power input. Connected internally to the source of the Buck1 P-channel switch.
Should be closely decoupled to PGND1 with a 4.7μF or greater capacitor.
DC-DC2 (Buck2) power input. Connected internally to the source of the Buck2 P-channel switch.
Should be closely decoupled to PGND2 with a 4.7μF or greater capacitor.
DC-DC2 (Buck2) power ground. Connected internally to the source of the Buck2 N-channel syn-
chronous rectifier. Connect PGND2 to PGND1 and AGND as close as possible to the device.
Exposed paddle (bottom). Connect to ground as close as possible to the device.
2603.2008.06.1.0
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