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AAT2554 参数 Datasheet PDF下载

AAT2554图片预览
型号: AAT2554
PDF下载: 下载PDF文件 查看货源
内容描述: 用于便携式应用的总电源解决方案 [Total Power Solution for Portable Applications]
分类和应用: 便携式
文件页数/大小: 33 页 / 880 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
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AAT2554  
Total Power Solution for Portable Applications  
VINB  
VINB  
ADP  
C1  
4.7µF  
U1  
VBAT  
ADP  
16  
11  
9
8
1
2
VINB  
BAT  
OUTA  
LX  
5
VOUTA  
L1  
R4  
1K  
ADP  
STAT  
VINA  
ENA  
ENB  
C3  
4.7µF  
VOUTA  
VOUTB  
C8  
15  
1
VOUTB  
D1  
4
FB  
R2  
118K  
ENA  
13  
3
14  
12  
10  
2
R5  
100K  
C4  
4.7µF  
GND  
GND  
VINB  
VINA  
100pF  
C7  
2.2µF  
FB  
JP2  
6
C6  
2.2µF  
C5  
2.2µF  
R3  
59K  
R6  
100K  
JP3  
C8 optional for  
enhanced step-  
down converter  
transient  
3
2
1
EN_BAT GND  
ADP  
7
ISET  
GND  
response  
ENA  
R7  
100K  
JP1  
3
2
1
AAT2554  
ENB  
R1  
8.06K  
ENB  
3
2
1
EN_BAT  
GND  
EN_BAT  
Figure 5: AAT2554 Evaluation Board Schematic.  
3. The feedback pin (Pin 1) should be separate  
from any power trace and connect as closely as  
possible to the load point. Sensing along a high-  
current load trace will degrade DC load regula-  
tion. Feedback resistors should be placed as  
closely as possible to the FB pin (Pin 1) to mini-  
mize the length of the high impedance feedback  
trace. If possible, they should also be placed  
away from the LX (switching node) and inductor  
to improve noise immunity.  
4. The resistance of the trace from the load return  
GND (Pins 2, 10, 12, and 14) should be kept to  
a minimum. This will help to minimize any error  
in DC regulation due to differences in the poten-  
tial of the internal signal ground and the power  
ground.  
Printed Circuit Board Layout  
Considerations  
For the best results, it is recommended to physi-  
cally place the battery pack as close as possible to  
the AAT2554 BAT pin. To minimize voltage drops  
on the PCB, keep the high current carrying traces  
adequately wide. Refer to the AAT2554 evaluation  
board for a good layout example (see Figures 6  
and 7). The following guidelines should be used to  
help ensure a proper layout.  
1. The input capacitors (C1, C3, C7) should con-  
nect as closely as possible to ADP (Pin 11),  
VINA (Pin 4), and VINB (Pin 16).  
2. C4 and L1 should be connected as closely as  
possible. The connection of L1 to the LX pin  
should be as short as possible. Do not make the  
node small by using narrow trace. The trace  
should be kept wide, direct, and short.  
5. A high density, small footprint layout can be  
achieved using an inexpensive, miniature, non-  
shielded, high DCR inductor.  
26  
2554.2007.01.1.2  
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