AAT2552
Total Power Solution for Portable Applications
1. The input capacitors (C1, C6) should connect as
closely as possible to ADP, INA, and INB. It is pos-
R4 Standard 1% Values
(R5 = 59kΩ)
sible to use two input capacitors for INA and INB.
2. C4 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible. Do not make the
node small by using narrow trace. The trace
should be kept wide, direct, and short.
VOUT (V)
R4 (kΩ)
3.3
2.8
2.5
2.0
1.8
1.5
97.6
75.0
60.4
36.5
26.7
12.4
3. The feedback pin should be separate from any
power trace and connect as closely as possible
to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
Feedback resistors should be placed as closely
as possible to the FBB pin to minimize the length
of the high impedance feedback trace. If possi-
ble, they should also be placed away from the
LX (switching node) and inductor to improve
noise immunity.
4. The resistance of the trace from PGND should
be kept to a minimum. This will help to minimize
any error in DC regulation due to differences in
the potential of the internal signal ground and
the power ground.
Table 4: Adjustable Resistor Values for the LDO.
Printed Circuit Board Layout
Considerations
For the best results, it is recommended to physi-
cally place the battery pack as close as possible to
the AAT2552 BAT pin. To minimize voltage drops
on the PCB, keep the high current carrying traces
adequately wide. Refer to the AAT2552 evaluation
board for a good layout example (see Figures 6
and 7). The following guidelines should be used to
help ensure a proper layout.
5. A high density, small footprint layout can be
achieved using an inexpensive, miniature, non-
shielded, high DCR inductor.
2552.2007.04.1.0
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