PRODUCT DATASHEET
AAT2514
SwitchRegTM
Dual Channel 600mA Step-Down Converter
Therefore:
To minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C1) can be seen in the
evaluation board layout in Figure 3. A laboratory test set-
up typically consists of two long wires running from the
bench power supply to the evaluation board input voltage
pins. The inductance of these wires, along with the low-
ESR ceramic input capacitor, can create a high Q net-work
that may affect converter performance. This problem
often becomes apparent in the form of excessive ringing
in the output voltage during load transients. Errors in the
loop phase and gain measurements can also result. Since
the inductance of a short PCB trace feeding the input volt-
age is significantly lower than the power leads from the
bench power supply, most applications do not exhibit this
problem. In applications where the input power source
lead inductance cannot be reduced to a level that does
not affect the converter performance, a high ESR tanta-
lum or aluminum electrolytic should be placed in parallel
with the low ESR, ESL bypass ceramic. This dampens the
high Q network and stabilizes the system.
2.5
m
L =
= 2.2µH
With these adaptive settings, a 2.2μH inductor can be
used for all output voltages from 0.6V to 5V.
Input Capacitor Selection
The input capacitor reduces the surge current drawn
from the input and switching noise from the device. The
input capacitor impedance at the switching frequency
shall be less than the input source impedance to prevent
high frequency switching current passing to the input.
The calculated value varies with input voltage and is a
maximum when VIN is double the output voltage.
VO
⎛
VO ⎞
VIN
· 1 -
⎝
VIN
⎠
CIN =
⎛ VPP
⎝ IO
⎞
- ESR ·FS
⎠
VO
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
for VIN = 2 · VO
VIN
4
Output Capacitor Selection
1
CIN(MIN)
=
⎛ VPP
⎞
The function of output capacitance is to store energy to
attempt to maintain a constant voltage. The energy is
stored in the capacitor’s electric field due to the voltage
applied.
- ESR · 4 · FS
⎝ IO
⎠
A low ESR input capacitor sized for maximum RMS cur-
rent must be used. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of their low
ESR and small temperature coefficients. A 22μF ceramic
capacitor for most applications is sufficient. A large value
may be used for improved input voltage filtering.
The value of output capacitance is generally selected to
limit output voltage ripple to the level required by the
specification. Since the ripple current in the output induc-
tor is usually determined by L, VOUT, and VIN, the series
impedance of the capacitor primarily determines the out-
put voltage ripple. The three elements of the capacitor
that contribute to its impedance (and output voltage
ripple) are equivalent series resistance (ESR), equivalent
series inductance (ESL), and capacitance (C). The out-
put voltage droop due to a load transient is dominated by
the capacitance of the ceramic output capacitor. During a
step increase in load current, the ceramic output capaci-
tor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The relationship of the output volt-
age droop during the three switching cycles to the output
capacitance can be estimated by:
The maximum input capacitor RMS current is:
VO
⎛
VO ⎞
IRMS = IO ·
· 1 -
⎝
VIN
VIN
⎠
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current
VO
⎛
VO ⎞
VIN ⎠
1
2
· 1 -
⎝
=
D · (1 - D) = 0.52 =
IO
VIN
IRMS(MAX)
=
2
3 · ΔILOAD
=
COUT
V
DROOP · FS
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2514.2008.02.1.1
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ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
