欢迎访问ic37.com |
会员登录 免费注册
发布采购

AAT2512IWP-AA-T1 参数 Datasheet PDF下载

AAT2512IWP-AA-T1图片预览
型号: AAT2512IWP-AA-T1
PDF下载: 下载PDF文件 查看货源
内容描述: 双400毫安高频降压转换器 [Dual 400mA High Frequency Buck Converter]
分类和应用: 转换器稳压器开关式稳压器或控制器电源电路开关式控制器
文件页数/大小: 20 页 / 732 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
 浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第9页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第10页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第11页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第12页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第14页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第15页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第16页浏览型号AAT2512IWP-AA-T1的Datasheet PDF文件第17页  
AAT2512  
Dual 400mA High Frequency Buck Converter  
Given the total losses, the maximum junction tem-  
perature can be derived from the θJA for the  
TDFN33-12 package which is 50°C/W.  
Thermal Calculations  
There are three types of losses associated with the  
AAT2512 converter: switching losses, conduction  
losses, and quiescent current losses. Conduction  
losses are associated with the RDS(ON) characteristics  
of the power output switching devices. Switching  
losses are dominated by the gate charge of the  
power output switching devices. At full load, assum-  
ing continuous conduction mode (CCM), a simplified  
form of the dual converter losses is given by:  
TJ(MAX)  
= PTOTAL · ΘJA + TAMB  
PCB Layout  
The following guidelines should be used to insure a  
proper layout.  
IO12 · (RDSON(HS) · VO1 + RDSON(LS) · [VIN -VO1])  
1. Due to the pin placement of VIN for both con-  
verters, proper decoupling is not possible with  
just one input capacitor. The large input capaci-  
tor C3 should connect as closely as possible to  
VP and GND, as shown in Figure 4. The addi-  
tional input bypass capacitor C8 is necessary for  
proper high frequency decoupling of the second  
converter.  
PTOTAL  
=
+
VIN  
IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])  
VIN  
+ (tsw · F · [IO1 + IO2] + 2 · IQ) · VIN  
2. The output capacitor and inductor should be  
connected as closely as possible. The connec-  
tion of the inductor to the LX pin should also be  
as short as possible.  
3. The feedback trace should be separate from any  
power trace and connect as closely as possible  
to the load point. Sensing along a high-current  
load trace will degrade DC load regulation. If  
external feedback resistors are used, they  
should be placed as closely as possible to the  
FB pin. This prevents noise from being coupled  
into the high impedance feedback node.  
IQ is the AAT2512 quiescent current for one chan-  
nel and tsw is used to estimate the full load switch-  
ing losses.  
For the condition where channel one is in dropout  
at 100% duty cycle, the total device dissipation  
reduces to:  
PTOTAL = IO12 · RDSON(HS)  
4. The resistance of the trace from the load return  
to GND should be kept to a minimum. This will  
help to minimize any error in DC regulation due  
to differences in the potential of the internal sig-  
nal ground and the power ground.  
IO22 · (RDSON(HS) · VO2 + RDSON(LS) · [VIN -VO2])  
+
VIN  
+ (tsw · F · IO2 + 2 · IQ) · VIN  
5. For good thermal coupling, PCB vias are required  
from the pad for the TDFN paddle to the ground  
plane. The via diameter should be 0.3mm to  
0.33mm and positioned on a 1.2 mm grid.  
Since RDS(ON), quiescent current, and switching  
losses all vary with input voltage, the total losses  
should be investigated over the complete input  
voltage range.  
2512.2006.06.1.4  
13