AAT2510
Dual 400mA, 1MHz Step-Down DC-DC Converter
The equation below solves for input capacitor size
capacitor RMS current ripple are a maximum at
50% duty cycle.
for both channels. It makes the worst-case
assumptions that both converters are operating at
50% duty cycle and are synchronized.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT2510. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
the stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps
the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
1
CIN =
⎛
VPP
⎝IO1 + IO2
⎞
⎠
- ESR • 4 • FS
The proper placement of the input capacitor (C3
and C8) can be seen in the evaluation board layout
in Figure 4. Since decoupling must be as close to
the input pins as possible, it is necessary to use
two decoupling capacitors. C3 provides the bulk
capacitance required for both converters, while C8
is a high frequency bypass capacitor for the second
channel (see C3 and C8 placement in Figure 4).
Because the AAT2510 channels will generally
operate at different duty cycles and are not syn-
chronized, the actual ripple will vary and be less
than the ripple (VPP) used to solve for the input
capacitor in the equation above.
Always examine the ceramic capacitor DC voltage
coefficient characteristics when selecting the prop-
er value. For example, the capacitance of a 10µF
6.3V X5R ceramic capacitor with 5V DC applied is
actually about 6µF.
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance.
The maximum input capacitor RMS current is:
VO1
VIN
⎛
⎝
VO1
VIN
⎞
⎠
VO2
VIN
⎛
· 1 -
VO2
VIN
⎞
⎠
⎛
⎞
⎛
⎞
IRMS = IO1
·
·
1 -
+ IO2
·
This problem often becomes apparent in the form
of excessive ringing in the output voltage during
load transients. Errors in the loop phase and gain
measurements can also result.
⎝
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current of
both converters combined.
Since the inductance of a short printed circuit board
trace feeding the input voltage is significantly lower
than the power leads from the bench power supply,
most applications do not exhibit this problem.
IO1(MAX) + IO2(MAX)
IRMS(MAX)
=
2
In applications where the input power source lead
inductance cannot be reduced to a level that does
not affect converter performance, a high ESR tan-
talum or aluminum electrolytic capacitor should be
placed in parallel with the low ESR, ESL bypass
ceramic capacitor. This dampens the high Q net-
work and stabilizes the system.
This equation also makes the worst-case assump-
tion that both converters are operating at 50% duty
cycle and are synchronized. Since the converters
are not synchronized and are not both operating at
50% duty cycle, the actual RMS current will always
be less than this. Losses associated with the input
ceramic capacitor are typically minimal.
Output Capacitor
VO
⎛
⎝
VO
⎞
⎠
·
1 -
The term
appears in both the input
VIN
VIN
The output capacitor limits the output ripple and
provides holdup during large load transitions. A
4.7µF to 10µF X5R or X7R ceramic capacitor typi-
cally provides sufficient bulk capacitance to stabi-
voltage ripple and input capacitor RMS current
equations. It is a maximum when VO is twice VIN.
This is why the input voltage ripple and the input
2510.2005.08.1.5
11
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