PRODUCT DATASHEET
AAT2504178
SystemPowerTM
Adjustable 3-Channel Regulator
3. The feedback trace should be separate from any
power trace and connect as closely as possible to the
load point. Sensing along a high-current load trace
will degrade DC load regulation. Feedback resistors
should be placed as closely as possible to VOUT to
minimize the length of the high impedance feedback
trace. If possible, they should also be placed away
from the LX (switching node) and inductor to improve
noise immunity.
4. The resistance of the trace from the load return to
the PGND should be kept to a minimum. This will
help to minimize any error in DC regulation due to
differences in the potential of the internal signal
ground and the power ground.
Layout
The suggested PCB layout for the AAT2504 is shown in
Figures 1 and 2. The following guidelines should be used
to help ensure a proper layout.
1. The input capacitors (C4, C7, C8, and C9) should
connect as closely as possible to VIN, VLDOA,
VLDOB, VP, and PGND.
2. The output capacitor (C5, and C6) of the LDOs con-
nect as closely as possible to OUT. C2 and L1 should
be connected as closely as possible. The connection
of L1 to the LX pin should be as short as possible. Do
not make the node small by using a narrow trace.
The trace should be kept wide, direct, and short.
5. Ensure all ground pins are tied to the ground plane.
No pins should be left floating. For maximum power
dissipation, it is recommended that the exposed
pad (EP) must be soldered to a good conductive
PCB ground plane layer to further increase local
heat dissipation.
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