PRODUCT DATASHEET
AAT2503178
SystemPowerTM
Adjustable 3-Channel Regulator
VOUT exceeding VIN for brief amounts of time during nor-
mal operation, the use of a larger value CIN capacitor is
highly recommended. A larger value of CIN with respect
to COUT will effect a slower CIN decay rate during shut-
down, thus preventing VOUT from exceeding VIN. In appli-
cations where there is a greater danger of VOUT exceeding
VIN for extended periods of time, it is recommended to
place a Schottky diode across VIN to VOUT (connecting the
cathode to VIN and anode to VOUT). The Schottky diode
forward voltage should be less than 0.45V.
The maximum continuous output current for the AAT2503
is a function of the package power dissipation and the
input-to-output voltage drop across the LDO regulator.
To determine the maximum output current for a given
output voltage, refer to the following equation. This
calculation accounts for the total power dissipation of the
LDO regulator, including that caused by ground current.
PD(MAX) = [(VIN - VOUTA)IOUTA + (VIN · IGND)] + [(VIN - VOUTB)IOUTB + (VIN · IGND)]
Layout
Thermal Considerations and
The suggested PCB layout for the AAT2503 is shown in
Figures 2 and 3. The following guidelines should be used
to help ensure a proper layout.
High Output Current Applications
The LDOs of the AAT2503 are designed to deliver con-
tinuous output load currents of 150mA each under nor-
mal operation. This is desirable for circuit applications
where there might be a brief high in-rush current during
a power-on event.
1. The input capacitors (C4, C7, C8, and C9) should
connect as closely as possible to VIN and PGND.
2. The output capacitor (C5, and C6) of the LDOs con-
nect as closely as possible to OUT. C2 and L1 should
be connected as closely as possible. The connection
of L1 to the LX pin should be as short as possible. Do
not make the node small by using a narrow trace.
The trace should be kept wide, direct, and short.
3. The feedback trace should be separate from any
power trace and connect as closely as possible to the
load point. Sensing along a high-current load trace
will degrade DC load regulation. Feedback resistors
should be placed as closely as possible to VOUT to
minimize the length of the high impedance feedback
trace. If possible, they should also be placed away
from the LX (switching node) and inductor to improve
noise immunity.
The limiting characteristic for the maximum output load
current safe operating area is essentially package power
dissipation and the internal preset thermal limit of the
device. In order to obtain high operating currents, care-
ful device layout and circuit operating conditions need to
be taken into account.
The following discussions will assume the LDO regulator is
mounted on a printed circuit board utilizing the minimum
recommended footprint as stated in the layout consider-
ations section of this document. At any given ambient
temperature (TA), the maximum package power dissipa-
tion can be determined by the following equation:
4. The resistance of the trace from the load return to
the PGND should be kept to a minimum. This will
help to minimize any error in DC regulation due to
differences in the potential of the internal signal
ground and the power ground.
5. Ensure all ground pins are tied to the ground plane.
No pins should be left floating. For maximum power
dissipation, it is recommended that the exposed pad
must be soldered to a good conductive PCB ground
plane layer to further increase local heat dissipation.
TJ(MAX) - TA
θJA
PD(MAX)
=
Constants for the AAT2503 are TJ(MAX) (the maximum
junction temperature for the device, which is 125°C) and
θJA = 50°C/W (the package thermal resistance). Typically,
maximum conditions are calculated at the maximum
operating temperature of TA = 85°C and under normal
ambient conditions where TA = 25°C. Given TA = 85°C,
the maximum package power dissipation is 800mW. At TA
= 25°C, the maximum package power dissipation is 2W.
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