欢迎访问ic37.com |
会员登录 免费注册
发布采购

AAT2500IWP-AT-T1 参数 Datasheet PDF下载

AAT2500IWP-AT-T1图片预览
型号: AAT2500IWP-AT-T1
PDF下载: 下载PDF文件 查看货源
内容描述: 1MHz的降压转换器/ LDO稳压器 [1MHz Step-Down Converter/LDO Regulator]
分类和应用: 转换器稳压器
文件页数/大小: 26 页 / 862 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
 浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第15页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第16页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第17页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第18页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第20页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第21页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第22页浏览型号AAT2500IWP-AT-T1的Datasheet PDF文件第23页  
AAT2500  
1MHz Step-Down Converter/LDO Regulator  
Given the total losses, the maximum junction tem-  
perature can be derived from the θJA for the  
TDFN/STDFN33-12 package which is 50°C/W.  
Thermal Calculations  
There are three types of losses associated with the  
AAT2500 step-down converter: switching losses,  
conduction losses, and quiescent current losses.  
Conduction losses are associated with the RDS(ON)  
characteristics of the power output switching  
devices. Switching losses are dominated by the  
gate charge of the power output switching devices.  
At full load, assuming continuous conduction mode  
(CCM), a simplified form of the step-down convert-  
er and LDO losses is given by:  
TJ(MAX)  
=
PTOTAL  
·
Θ
JA + TAMB  
PCB Layout  
The following guidelines should be used to ensure  
a proper layout.  
1. The input capacitor C2 should connect as  
closely as possible to VP and PGND, as shown  
in Figure 4.  
IOBUCK2 · (RDSON(HS) · VOBUCK + RDSON(LS) · [VIN - VOBUCK])  
PTOTAL  
=
VIN  
2. The output capacitor and inductor should be  
connected as closely as possible. The connec-  
tion of the inductor to the LX pin should also be  
as short as possible.  
3. The feedback trace should be separate from  
any power trace and connect as closely as  
possible to the load point. Sensing along a  
high-current load trace will degrade DC load  
regulation. If external feedback resistors are  
used, they should be placed as closely as pos-  
sible to the FB pin. This prevents noise from  
being coupled into the high impedance feed-  
back node.  
4. The resistance of the trace from the load return  
to GND should be kept to a minimum. This will  
help to minimize any error in DC regulation due  
to differences in the potential of the internal sig-  
nal ground and the power ground.  
5. For good thermal coupling, PCB vias are  
required from the pad for the TDFN/STDFN pad-  
dle to the ground plane. The via diameter should  
be 0.3mm to 0.33mm and positioned on a  
1.2mm grid.  
+ (tsw · F · IOBUCK + IQBUCK + IQLDO) · VIN + IOLDO · (VIN - VOLDO  
)
IQBUCK is the step-down converter quiescent cur-  
rent and IQLDO is the LDO quiescent current. The  
term tsw is used to estimate the full load step-down  
converter switching losses.  
For the condition where the buck converter is in  
dropout at 100% duty cycle, the total device dissi-  
pation reduces to:  
PTOTAL = IOBUCK2 · RDSON(HS) + IOLDO · (VIN - VOLDO  
+ (IQBUCK + IQLDO) · VIN  
)
Since RDS(ON), quiescent current, and switching  
losses all vary with input voltage, the total losses  
should be investigated over the complete input  
voltage range.  
6. LDO bypass capacitor (C5) should be connected  
directly between pins 7 (BYP) and 8 (GND)  
2500.2006.05.1.16  
19  
 复制成功!