AAT2513
Dual 600mA Step-Down
Converter with Synchronization
Pin Descriptions
Pin #
Symbol
Function
1
PS
Phase shift pin. Logic high enables the PS feature which forces the two converters
to operate 180° out of phase when both are in forced PWM mode.
Analog ground. Return the feedback resistive divider to this ground. See section on
PCB layout guidelines and evaluation board layout diagram.
2
AGND
4, 3
FB1, FB2
Feedback input pins. An external resistive divider ties to each and programs the
respective output voltage to the desired value.
5, 16
6, 15
7, 14
8, 13
VIN1, VIN2
N/C
LX1, LX2
Input supply voltage pins. Must be closely decoupled to the respective PGND.
Not connected
Output switching nodes that connect to the respective output inductor.
Main power ground return. Connect to the input and output capacitor return. See
section on PCB layout guidelines and evaluation board layout diagram.
Converter enable input pins. A logic high enables the converter channel. A logic low
forces the channel into shutdown mode, reducing the channel supply current to less
than 1µA. This pin should not be left floating. When not actively controlled, this pin
can be tied directly to VIN and/or VCC.
PGND1, PGND2
10, 9
EN1, EN2
11
12
VCC
MODE/SYNC
Control circuit power supply. Connect to the higher voltage of VIN1 or VIN2.
Logic low enables automatic light load mode for optimized efficiency throughout the
entire load range. Logic high forces low noise PWM operation under all operating
conditions. Connect to an external clock for synchronization (PWM only).
Exposed paddle (bottom). Use properly sized vias for thermal coupling to the
ground plane. See section on PCB layout guidelines.
EP
Pin Configuration
QFN33-16
(Top View)
1
2
3
4
12
11
10
9
PS
AGND
FB2
MODE/SYNC
VCC
EN1
EN2
FB1
2
2513.2007.04.1.1
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
