PRODUCT DATASHEET
AAT2158
SwitchRegTM
1.5A Low Noise Step-Down Converter
The maximum input capacitor RMS current is:
Component Selection
VO
VIN
⎛
VO ⎞
VIN ⎠
IRMS = IO ·
· 1 -
⎝
Inductor Selection
The step-down converter uses peak current mode con-
trol with slope compensation to maintain stability for
duty cycles greater than 50%. The output inductor value
must be selected so the inductor current down slope
meets the internal slope compensation requirements.
The inductor should be set equal to the output voltage
numeric value in μH. This guarantees that there is suf-
ficient internal slope compensation.
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
VO
VIN
⎛
VO ⎞
VIN ⎠
1
2
· 1 -
⎝
=
D · (1 - D) = 0.52 =
for VIN = 2 · VO
Manufacturer’s specifications list both the inductor DC
current rating, which is a thermal limitation, and the
peak current rating, which is determined by the satura-
tion characteristics. The inductor should not show any
appreciable saturation under normal load conditions.
Some inductors may meet the peak and average current
ratings yet result in excessive losses due to a high DCR.
Always consider the losses associated with the DCR and
its effect on the total converter efficiency when selecting
an inductor.
IO
IRMS(MAX)
=
2
VO
VIN
⎛
⎝
VO
VIN
⎞
⎠
·
1 -
The term
appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2158. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The 3.3μH CDRH4D28 series Sumida inductor has a
49.2mΩ worst case DCR and a 1.57A DC current rating. At
full 1.5A load, the inductor DC loss is 97mW which gives
less than 1.5% loss in efficiency for a 1.5A, 3.3V output.
Input Capacitor
The proper placement of the input capacitor (C1) can be
seen in the evaluation board layout in the Layout section
of this datasheet (see Figure 2).
Select a 10μF to 22μF X7R or X5R ceramic capacitor for
the input. To estimate the required input capacitor size,
determine the acceptable input ripple level (VPP) and solve
for C. The calculated value varies with input voltage and
is a maximum when VIN is double the output voltage.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
VO
VIN
⎛
VO ⎞
VIN ⎠
· 1 -
⎝
CIN =
⎛ VPP
⎝ IO
⎞
- ESR ·FS
⎠
VO
VIN
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
for VIN = 2 · VO
4
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
1
CIN(MIN)
=
⎛ VPP
⎝ IO
⎞
⎠
- ESR · 4 · FS
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
Always examine the ceramic capacitor DC voltage coeffi-
cient characteristics when selecting the proper value. For
example, the capacitance of a 10μF, 6.3V, X5R ceramic
capacitor with 5.0V DC applied is actually about 6μF.
w w w . a n a l o g i c t e c h . c o m
2158.2008.02.1.2
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