PRODUCT DATASHEET
AAT2120
SwitchRegTM
500mA Low Noise Step-Down Converter
Given the total losses, the maximum junction tempera-
ture can be derived from the θJA for the STDFN22-8
package which is 50°C/W.
3. The feedback pin (Pin 4) should be separate from
any power trace and connect as closely as possible
to the load point. Sensing along a high-current load
trace will degrade DC load regulation. Feedback
resistors should be placed as closely as possible to
the FB pin (Pin 4) to minimize the length of the high
impedance feedback trace. If possible, they should
also be placed away from the LX (switching node)
and inductor to improve noise immunity.
TJ(MAX) = PTOTAL · ΘJA + TAMB
Layout
The suggested PCB layout for the AAT2120 in an
STDFN22-8 package is shown in Figures 2, 3, and 4. The
following guidelines should be used to help ensure a
proper layout.
4. The resistance of the trace from the load return to
PGND (Pin 8) and GND (Pin 3) should be kept to a
minimum. This will help to minimize any error in DC
regulation due to differences in the potential of the
internal signal ground and the power ground.
5. A high density, small footprint layout can be achieved
using an inexpensive, miniature, non-shielded, high
DCR inductor.
1. The input capacitor (C1) should connect as closely
as possible to VP (Pin 1), PGND (Pin 8), and GND
(Pin 3)
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin (Pin 7) should
be as short as possible. Do not make the node small
by using narrow trace. The trace should be kept
wide, direct and short.
U1
1
8
7
6
5
VIN
VP
PGND
LX
L1
LX
2
3
4
VIN
+VOUT
GND
FB
EN
C3
(optional)
100pF
R1
Adj.
N/C
C2
4.7μF
AAT2120
C1
4.7μF
R2
59kΩ
GND
GND
Figure 1: AAT2120 Schematic.
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2120.2008.02.1.2
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