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AAT1275ITP-5.0-T1 参数 Datasheet PDF下载

AAT1275ITP-5.0-T1图片预览
型号: AAT1275ITP-5.0-T1
PDF下载: 下载PDF文件 查看货源
内容描述: 升压转换器, USB电源开关 [Boost Converter with USB Power Switch]
分类和应用: 转换器开关电源开关升压转换器
文件页数/大小: 19 页 / 473 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
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AAT1275  
Boost Converter with USB Power Switch  
Due to the magnitude of the inductor ripple current,  
RDS(ON)IN is the input disconnect switch, RDS(ON)N is  
the high-side synchronous switch, RDS(ON)P is the  
low-side synchronous switch, and RDS(ON) is the  
current limit load switch.  
it cannot be neglected when analyzing the RDS(ON)  
power dissipation. Once the ripple current has  
been determined, the RMS current during the on  
and the off period can be calculated.  
PCB Layout Guidelines  
VO - VIN(MIN)  
VO  
The step-up converter performance can be  
adversely affected by poor layout. Possible impact  
includes high input and output voltage ripple, poor  
EMI performance, and reduced operating efficiency.  
Every attempt should be made to optimize the lay-  
out in order to minimize parasitic PCB effects (stray  
resistance, capacitance, inductance) and EMI cou-  
pling from the high frequency SW node.  
DMAX  
=
VIN(MIN) · DMAX  
L · FS  
IPP  
=
IO  
IP =  
A suggested PCB layout for the AAT1275 is shown  
in Figures 1 and 2. The following PCB layout guide-  
lines should be considered:  
1 - D  
IPP  
2
IPK = IP +  
1. Minimize the distance from capacitors C2 and  
C3 to the IC. This is especially true for the out-  
put capacitor C2, which conducts high ripple cur-  
rent associated with the step-up converter out-  
put capacitor.  
IV = IP - IPP  
2. Place the feedback resistor close to the output  
terminals. Route the output pin directly to resis-  
tor R2 to maintain good output regulation. R3  
should be routed close to the output GND pin  
and should not share a significant return path  
with output capacitor C2.  
3. Minimize the distance between L1 and the  
switching pin SW; minimize the size of the PCB  
area connected to the SW pin.  
2
(IP2 + IPK · IV + IV ) · DMAX  
IRMS(ON)  
=
3
(IP2 + IPK · IV + IV ) · (1 - DMAX  
)
2
IRMS(OFF)  
=
3
PTOTAL = IRMS(ON)2 · (RDS(ON)IN  
+
RDS(ON)N  
)
4. Maintain a ground plane and connect to the IC  
RTN pin(s), as well as the GND terminals of C1  
and C2.  
+
IRMS(OFF)2 · (RDS(ON)IN  
+
RDS(ON)P  
+
RDS(ON))  
TJ(MAX)  
=
P
TOTAL · θJA  
+ TAMB  
1275.2007.01.1.3  
13