PRODUCT DATASHEET
AAT1272
TM
SwitchReg
1.5A Step-Up Current Regulator for Flash LEDs
requires a master to initiate all the communications with
target devices. The AAT1272 is a target device and only
supports the write protocol. The AAT1272 is manufac-
tured with a target device address of 0x37 (Hex). See
Figure 2 for the I2C interface diagram.
Flash Safety Timeout
The AAT1272 includes a timer circuit that enables the
flash current for a programmed period of time. This fea-
ture eliminates the need for an external, housekeeping
baseband controller to contain a safety delay routine. It
also serves as a protection feature to minimize thermal
issues with the flash LEDs in the event an external con-
troller’s flash software routine experiences hang-up or
freeze. The flash safety timeout, T can be calculated by
the following equation:
I2C START and STOP Conditions
START and STOP conditions are always generated by the
master. Prior to initiating a START, both the SDA and SCL
pins are in idle mode (idle mode is when there is no
activity on the bus and SDA and SCL are pulled high by
the external pull-up resistors). A START condition occurs
when the master strobes the SDA line low and after a
short period strobes the SCL line low. A START condition
acts as a signal to all ICs that transmission activity is
about to occur on the I2C bus. A STOP condition, as
shown in Figure 2, is when master releases the bus and
SCL changes from low to high followed by SDA low-to-
high transition. The master does not issue an
ACKNOWLEDGE and releases the SCL and SDA pins.
T = 7.98s/μF · CT
Where T is in seconds and CT is the capacitance of the
timer capacitor in ꢀF.
For example, using a 47nF capacitor for CT sets the flash
timeout to:
Flash Safety Timeout = 7.98s/μF · 0.047μF = 375ms
The relationship between the flash safety timeout and
the capacitance of the timer capacitor is illustrated in
Figure 1.
I2C Address Bit Map
1200
1000
800
600
400
200
0
Figure 4 illustrates the address bit transfer. The 7-bit
address is transferred with the Most Significant Bit
(MSB) first and is valid when SCL is high. This is followed
by the R/W bit in the Least Significant Bit (LSB) location.
The R/W bit on the eighth bit determines the direction of
the transfer (a '1' for read or a '0' for write). The
AAT1272 is a write-only device and the R/W bit must be
set low. The Acknowledge bit (ACK) is set to low by the
AAT1272 to acknowledge receipt of the address.
0
20
40
60
80
100
120
140
I2C Register Address/Data Bit Map
CT Capacitor (nF)
Figure 5 illustrates the Register Address or the serial data
bit transfer. The 8-bit data is always transferred most
significant bit first and is valid when SCL is high. The
Acknowledge bit (ACK) is set low by the AAT1272 to
acknowledge receipt of the register address or the data.
Figure 1: Flash Safety Timeout
vs. Timer Capacitor.
I2C Serial Interface
The AAT1272 is fully compliant with the industry-stan-
dard I2C interface. The I2C two-wire communications bus
consists of SDA and SCL lines. SDA provides data, while
SCL provides clock synchronization with speed up to
400kHz. SDA data transfers device address followed by
a register address and data bits sequence. When using
the I2C interface, EN is pulled high to enable the device
or low to disable the device. The I2C serial interface
I2C Acknowledge Bit (ACK)
The Acknowledge bit is the ninth bit of each transfer on
the SDA line. It is used to send back a confirmation to
the master that the data has been received properly by
the target device. For each ACK to take place, the mas-
ter must first release the SDA line, and then the target
device will pull the SDA line low, as shown in Figures 1,
4, and 5.
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1272.2009.04.1.2
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