PRODUCT DATASHEET
AAT1189
TM
SwitchReg
High Voltage Step-Down Regulator
2. C2, L1, D2, C8 and C9 should be placed as close as
possible to minimize any parasitic inductance in the
switched current path which generates a large volt-
age spike during the switching interval. The connec-
tion of inductor to switching node should be as short
as possible.
3. The feedback trace or FB pin should be separated
from any power trace and connected as close as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
4. The resistance of the trace from the load returns to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
Over-Current Protection
The controller provides true-load DC output current
sensing which protects the load and limits component
stresses. The output current is sensed through the DC
resistance in the output inductor (DCR). The controller
reduces the operating frequency when an over-current
condition is detected; limiting stresses and preventing
inductor saturation. This allows the smallest possible
inductor for a given output load. A small resistor divider
may be necessary to adjust the over-current threshold
and compensate for variation in inductor DCR.
The preset current limit threshold is triggered when the
differential voltage from RS to OS exceeds 100mV
(nominal).
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
Layout Considerations
6. The critical small signal components include feed-
back components, and compensation components
should be placed close to the FB and COMP pins. The
feedback resistors should be located as close as pos-
sible to the FB pin with its ground tied directly to the
signal ground plane which is separated from power
ground plane.
7. C4 should be connected close to the RS and OS pins,
while R1 should be connected close to the inductor.
8. For good thermal coupling, PCB vias are required
from the exposed pad (EP) for the TDFN paddle to the
bottom plane. The EP is internally connected to IN.
The suggested PCB layout for the AAT1189 is shown in
Figures 5 and 6. The following guidelines should be used
to help ensure a proper layout.
1. The power input capacitors (C1 and C12) should be
connected as close as possible to high voltage input
pin (IN) and power ground.
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