AAT1162
12V, 1.5A Step-Down DC/DC Converter
Pin Descriptions
Pin #
Symbol Function
1, 2, EP2
LX
Power switching node. LX is the drain of the internal P-channel switch and N-channel syn-
chronous rectifier. Connect the output inductor to the two LX pins and to EP2. A large
exposed copper pad under the package should be used for EP2.
3, 12
4, 5
N/C
IN
Not connected.
Power source input. Connect IN to the input power source. Bypass IN to DGND with a
22µF or greater capacitor. Connect both IN pins together as close to the IC as possible. An
additional 100nF ceramic capacitor should also be connected between the two IN pins and
DGND, pin 6
6, 13,
14, EP1
DGND
AIN
Exposed Pad 1 Digital Ground, DGND. The exposed thermal pad (EP1) should be connected
to board ground plane and pins 6, 13, and 14. The ground plane should include a large
exposed copper pad under the package for thermal dissipation (see package outline).
Internal analog bias input. AIN supplies internal power to the AAT1162. Connect AIN to the
input source voltage and bypass to AGND with a 0.1µF or greater capacitor. For additional
noise rejection, connect to the input power source through a 10Ω or lower value resistor.
Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The
internal circuitry of the AAT1162 is powered from LDO. Do not draw external power from LDO.
Bypass LDO to AGND with a 1µF or greater capacitor.
Output voltage feedback input. FB senses the output voltage for regulation control. For fixed
output versions, connect FB to the output voltage. For adjustable versions, drive FB from the
output voltage through a resistive voltage divider. The FB regulation threshold is 0.6V.
Control compensation node. Connect a series RC network from COMP to AGND, R = 51k
and C = 270pF.
7
8
LDO
FB
9
10
COMP
11
15
AGND
EN
Analog signal ground. Connect AGND to PGND at a single point as close to the IC as possible.
Active high enable input. Drive EN high to turn on the AAT1162; drive it low to turn it off. For
automatic startup, connect EN to IN through a 4.7kΩ resistor. EN must be biased high, biased
low, or driven to a logic level by an external source. Do not let the EN pin float when the
device is powered.
16
PGND
Power ground. Connect AGND to PGND at a single point as close to the IC as possible.
Pin Configuration
TDFN34-16
(Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
EN
LX
LX
EP2
EP1
N/C
IN
DGND
DGND
N/C
IN
AGND
COMP
FB
DGND
AIN
LDO
2
1162.2007.09.1.2
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
