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AAT1162 参数 Datasheet PDF下载

AAT1162图片预览
型号: AAT1162
PDF下载: 下载PDF文件 查看货源
内容描述: 12V , 1.5A降压型DC / DC转换器 [12V, 1.5A Step-Down DC/DC Converter]
分类和应用: 转换器
文件页数/大小: 16 页 / 626 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
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AAT1162  
12V, 1.5A Step-Down DC/DC Converter  
Max DCR  
(mΩ)  
Rated DC  
Size WxLxH  
(mm)  
Manufacturer  
Part Number  
L (µH)  
Current (A)  
Sumida  
Sumida  
Coilcraft  
CDRH103RNP-2R2N  
CDR7D43MNNP-3R7NC  
MSS1038-382NL  
2.2  
3.7  
3.8  
16.9  
18.9  
13  
5.10  
4.3  
4.25  
10.3x10.5x3.1  
7.6x7.6x4.5  
10.2x7.7x3.8  
Table 2: Typical Surface Mount Inductors.  
4. The input capacitors (C9 and C1) should be  
connected as close as possible to IN (Pins 4 and  
5) and DGND (Pin 6) to get good power filtering.  
5. Keep the switching node LX away from the  
sensitive FB node.  
6. The feedback trace for the FB pin should be  
separate from any power trace and connected  
as closely as possible to the load point.  
Sensing along a high-current load trace will  
degrade DC load regulation. The feedback  
resistors should be placed as close as possible  
to the FB pin (Pin 9) to minimize the length of  
the high impedance feedback trace.  
7. The output capacitors C3, 4, and 5 and L1  
should be connected as close as possible and  
there should not be any signal lines under the  
inductor.  
8. The resistance of the trace from the load return  
to the PGND (Pin 16) should be kept to a min-  
imum. This will help to minimize any error in  
DC regulation due to differences in the poten-  
tial of the internal signal ground and the power  
ground.  
Layout Guidance  
Figure 2 is the schematic for the evaluation board.  
When laying out the PC board, the following layout  
guideline should be followed to ensure proper  
operation of the AAT1162:  
1. Exposed pad EP1 must be reliably soldered to  
PGND/DGND/AGND. The exposed thermal  
pad should be connected to board ground  
plane and pins 6, 11, 13, 14 and 16. The ground  
plane should include a large exposed copper  
pad under the package for thermal dissipation.  
2. The power traces, including GND traces, the  
LX traces and the VIN trace should be kept  
short, direct and wide to allow large current  
flow. The L1 connection to the LX pins should  
be as short as possible. Use several via pads  
when routing between layers.  
3. Exposed pad pin EP2 must be reliably sol-  
dered to the LX pins 1 and 2. The exposed  
thermal pad should be connected to the board  
LX connection and the inductor L1 and also  
pins 1 and 2. The LX plane should include a  
large exposed copper pad under the package  
for thermal dissipation.  
1162.2007.09.1.2  
13  
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