PRODUCT DATASHEET
AAT1161
TM
SwitchReg
13.2V Input, 3A Step-Down Converter
To estimate the required input capacitor size, determine
the acceptable input ripple level (VPP) and solve for C.
The calculated value varies with input voltage and is a
maximum when VIN is double the output voltage.
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C6) can be seen in the
evaluation board layout in Figure 3. Additional noise fil-
tering for proper operation is accomplished by adding a
small 0.1µF capacitor on the IN pins (C2).
VO
⎛
VO ⎞
VIN ⎠
· 1 -
⎝
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result. Since the inductance of a
short PCB trace feeding the input voltage is significantly
lower than the power leads from the bench power sup-
ply, most applications do not exhibit this problem. In
applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
VIN
CIN =
⎛ VPP
⎝ IO
⎞
- ESR ·FOSC
⎠
VO
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
for VIN = 2 · VO
VIN
4
1
CIN(MIN)
=
⎛ VPP
⎝ IO
⎞
- ESR · 4 · FOSC
⎠
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 16V, X5R ceram-
ic capacitor with 12V DC applied is actually about
8.5μF.
The maximum input capacitor RMS current is:
VO
⎛
VO ⎞
VIN ⎠
IRMS = IO ·
· 1 -
⎝
Output Capacitor Selection
VIN
The output capacitor is required to keep the output volt-
age ripple small and to ensure regulation loop stability.
The output capacitor must have low impedance at the
switching frequency. Ceramic capacitors with X5R or
X7R dielectrics are recommended due to their low ESR
and high ripple current. The output ripple VOUT is deter-
mined by:
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current:
VO
VO
1
2
⎛
⎞
· 1 -
=
D · (1 - D) = 0.52 =
VIN
VIN
⎠
⎝
VOUT · (VIN - VOUT
)
⎛
1
⎞
for VIN = 2 · VO
∆VOUT
≤
· ESR +
⎝
VIN · FOSC · L
8 · FOSC · COUT
⎠
IO
2
IRMS(MAX)
=
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10μF to
47μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple. The output volt-
age droop due to a load transient is dominated by the
capacitance of the ceramic output capacitor. During a
step increase in load current, the ceramic output capac-
itor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match
the load current demand. The relationship of the output
VO
⎛
VO
1 -
⎞
⎠
·
VIN
⎝
VIN
The term
appears in both the input voltage rip-
ple and input capacitor RMS current equations and is at
maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT1161. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
w w w . a n a l o g i c t e c h . c o m
1161.2008.03.1.0
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