PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Pin Descriptions
Pin #
Symbol Function
Power switching node. LX is the drain of the internal P-channel switch and N-channel synchronous recti-
fier. Connect the output inductor to the two LX pins and to EP2. A large exposed copper pad under the
package should be used for EP2.
1, 2, EP2
3, 12
LX
N/C
IN
Not connected.
Power source input. Connect IN to the input power source. Bypass IN to DGND with a 10μF or greater
capacitor. Connect both IN pins together as close to the IC as possible. An additional 100nF ceramic ca-
pacitor should also be connected between the two IN pins and DGND, pin 6
4, 5
Exposed Pad 1 Digital Ground, DGND. The exposed thermal pad (EP1) should be connected to board
ground plane and pins 6 and 13. The ground plane should include a large exposed copper pad under the
package for thermal dissipation (see package outline).
Internal analog bias input. AIN supplies internal power to the AAT1160. Connect AIN to the input source
voltage and bypass to AGND with a 0.1μF or greater capacitor. For additional noise rejection, connect to
the input power source through a 10Ω or lower value resistor.
Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The internal cir-
cuitry of the AAT1160 is powered from LDO. Do not draw external power from LDO. Bypass LDO to AGND
with a 1μF or greater capacitor.
Output voltage feedback input. FB senses the output voltage for regulation control. For fixed output
versions, connect FB to the output voltage. For adjustable versions, drive FB from the output voltage
through a resistive voltage divider. The FB regulation threshold is 0.6V.
6, 13, EP1
DGND
AIN
7
8
9
LDO
FB
10
11
COMP
AGND
Control compensation node. Connect a series RC network from COMP to AGND, R = 50k and C = 150pF.
Analog signal ground. Connect AGND to PGND at a single point as close to the IC as possible.
Frequency select and synchronization input. Drive SYNC with a 500kHz to 1.6MHz signal to synchronize
the AAT1160 switching frequency to that signal. The Sync pin is also a mode select input. Drive SYNC
high or connect to the LDO pin for low-noise forced PWM mode. Drive SYNC low for high-efficiency PWM/
Light Load mode.
14
SYNC
Active high enable input. Drive EN high to turn on the AAT1160; drive it low to turn it off. For automatic
startup, connect EN to IN through a 4.7kΩ resistor. EN must be biased high, biased low, or driven to a
logic level by an external source. Do not let the EN pin float when the device is powered.
15
16
EN
PGND
Power ground. Connect AGND to PGND at a single point as close to the IC as possible.
Pin Configuration
TDFN34-16
(Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
EN
LX
LX
EP2
EP1
N/C
IN
SYNC
DGND
N/C
IN
AGND
DGND
AIN
LDO
COMP
FB
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1160.2007.11.1.1
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
