PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
the load current demand. The relationship of the output
voltage droop during the three switching cycles to the
output capacitance can be estimated by:
FOSC is the switching frequency and COUT is based on the
output capacitor calculation. The CCOMP value can be
determined from the following equation:
4
CCOMP (C7) =
3 · ΔILOAD
DROOP · FOSC
COUT
=
⎛FOSC
⎞
V
2πRCOMP (R5) ·
⎝ 10 ⎠
Layout Guidance
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients. The
internal voltage loop compensation also limits the mini-
mum output capacitor value to 22ꢁF. This is due to its
effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Figure 2 is the schematic for the evaluation board. When
laying out the PC board, the following layout guideline
should be followed to ensure proper operation of the
AAT1160:
1. Exposed pad EP1 must be reliably soldered to PGND/
DGND/AGND. The exposed thermal pad should be
connected to board ground plane and pins 6, 11, 13,
and 16. The ground plane should include a large
exposed copper pad under the package for thermal
dissipation.
2. The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
3. Exposed pad pin EP2 must be reliably soldered to
the LX pins 1 and 2. The exposed thermal pad
should be connected to the board LX connection and
the inductor L1 and also pins 1 and 2. The LX plane
should include a large exposed copper pad under the
package for thermal dissipation.
The maximum output capacitor RMS ripple current is
given by:
1
V
OUT · (VIN(MAX) - VOUT
)
IRMS(MAX)
=
·
L · FOSC · VIN(MAX)
2 · 3
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
Compensation
4. The input capacitors (C2 and C6) should be con-
nected as close as possible to IN (Pins 4 and 5) and
DGND (Pin 6) to get good power filtering.
5. Keep the switching node LX away from the sensitive
FB node.
6. The feedback trace for the FB pin should be separate
from any power trace and connected as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
The feedback resistors should be placed as close as
possible to the FB pin (Pin 9) to minimize the length
of the high impedance feedback trace.
7. The output capacitors C3, 4, and 5 and L1 should be
connected as close as possible and there should not
be any signal lines under the inductor.
The AAT1160 step-down converter uses peak current
mode control with slope compensation scheme to main-
tain stability with lower value inductors for duty cycles
greater than 50%. The regulation feedback loop in the
IC is stabilized by the components connected to the
COMP pin, as shown in Figure 1.
To optimize the compensation components, the following
equations can be used. The compensation resistor RCOMP
(R5) is calculated using the following equation:
2πVOUT · COUT
10GEA · GCOMP · VFB
·
FOSC
RCOMP (R5)=
Where VFB = 0.6V, GCOMP = 40.1734 and GEA = 9.091 ·
10-5.
8. The resistance of the trace from the load return to
the PGND (Pin 16) should be kept to a minimum.
This will help to minimize any error in DC regulation
due to differences in the potential of the internal
signal ground and the power ground.
w w w . a n a l o g i c t e c h . c o m
1160.2007.11.1.1
13
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
