PRODUCT DATASHEET
AAT1153
2A Step-Down Converter
In conclusion, in order to meet the requirement of out-
put voltage ripple small and regulation loop stability,
ceramic capacitors with X5R or X7R dielectrics are rec-
ommended due to their low ESR and high ripple current
ratings. The output ripple VOUT is determined by:
TJ(MAX) = PTOTAL · ΘJA + TAMB
Layout Guidance
When laying out the PC board, the following layout
guideline should be followed to ensure proper operation
of the AAT1153:
VOUT · (VIN - VOUT
)
1
⎛
⎞
⎠
ΔVOUT
≤
· ESR +
⎝
VIN · fOSC · L
8 · fOSC · COUT
1. The exposed pad (EP) must be reliably soldered to
the GND plane. A PGND pad below EP is strongly
recommended.
A 22μF ceramic capacitor can satisfy most applications.
Thermal Calculations
2. The power traces, including the GND trace, the LX
trace and the IN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several VIA pads when routing between layers.
3. The input capacitor (C1) should connect as closely
as possible to IN (Pin 2) and AGND (Pins 4 and 6) to
get good power filtering.
There are three types of losses associated with the
AAT1153 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the RDS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
4. Keep the switching node, LX (Pins 7 and 8) away
from the sensitive FB/OUT node.
5. The feedback trace or OUT pin (Pin 2) should be
separate from any power trace and connect as
closely as possible to the load point. Sensing along
a high-current load trace will degrade DC load regu-
lation. If external feedback resistors are used, they
should be placed as closely as possible to the FB pin
(Pin 5) to minimize the length of the high impedance
feedback trace.
6. The output capacitor C2 and L1 should be connected
as closely as possible. The connection of L1 to the LX
pin should be as short as possible and there should
not be any signal lines under the inductor.
7. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
IO2 · (RDSON(HS) · VO + RDSON(LS) · [VIN - VO])
PTOTAL
=
VIN
+ (tsw · F · IO + IQ) · VIN
IQ is the step-down converter quiescent current. The
term tsw is used to estimate the full load step-down con-
verter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
PTOTAL = IO2 · RDSON(HS) + IQ · VIN
Figures 4, 5 and 6 show an example of a layout with 4
layers. The internal 2 layers are SGND and PGND.
Since RDS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range. Given the
total losses, the maximum junction temperature can be
derived from the θJA for the DFN-10 package which is
45°C/W.
w w w . a n a l o g i c t e c h . c o m
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1153.2007.11.1.1
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
