PRODUCT DATASHEET
AAT1149A
TM
SwitchReg
2.2MHz FastTransient 400mA Step-Down Converter
The maximum input capacitor RMS current is:
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
VO
⎛
VO ⎞
VIN ⎠
IRMS = IO ·
· 1 -
⎝
VIN
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
Output Capacitor
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7μF to
10μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
VO
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
D · (1 - D) = 0.52 =
VIN
2
for VIN = 2 · VO
IO
IRMS(MAX)
=
The output voltage droop due to a load transient is dom-
inated by the capacitance of the ceramic output capaci-
tor. During a step increase in load current, the ceramic
output capacitor alone supplies the load current until the
loop responds. Within two or three switching cycles, the
loop responds and the inductor current increases to
match the load current demand. The relationship of the
output voltage droop during the three switching cycles to
the output capacitance can be estimated by:
2
VO
⎛
VO
1 -
⎞
⎠
·
VIN
⎝
VIN
The term
appears in both the input voltage rip-
ple and input capacitor RMS current equations and is a
maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for the
edges of pulsed current drawn by the AAT1149A. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
3 · ΔILOAD
=
COUT
V
DROOP · FS
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The proper placement of the input capacitor (C2) can be
seen in the evaluation board layout in Figure 1.
The internal voltage loop compensation also limits the
minimum output capacitor value to 4.7μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
The maximum output capacitor RMS ripple current is
given by:
1
V
OUT · (VIN(MAX) - VOUT
)
IRMS(MAX)
=
·
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
L · FS · VIN(MAX)
2 · 3
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
w w w . a n a l o g i c t e c h . c o m
10
1149A.2008.08.1.1
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