AAT1146
Fast Transient 400mA Step-Down Converter
The maximum input capacitor RMS current is:
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the
power leads from the bench power supply, most
applications do not exhibit this problem.
VO
VIN
⎛
· 1
⎝
VO
VIN
⎞
⎠
IRMS = IO
·
-
In applications where the input power source lead
inductance cannot be reduced to a level that does
not affect the converter performance, a high ESR
tantalum or aluminum electrolytic should be placed
in parallel with the low ESR, ESL bypass ceramic.
This dampens the high Q network and stabilizes
the system.
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current.
VO
VIN
⎛
· 1
⎝
VO
VIN
⎞
⎠
1
2
-
=
D
· (1 - D) = 0.52 =
Output Capacitor
The output capacitor limits the output ripple and
provides holdup during large load transitions. A
4.7μF to 10μF X5R or X7R ceramic capacitor typi-
cally provides sufficient bulk capacitance to stabi-
lize the output during large load transitions and has
the ESR and ESL characteristics necessary for low
output ripple.
for VIN = 2 x VO
IO
IRMS(MAX)
=
2
VO
VIN
⎛
1 -
VO
VIN
⎞
⎠
·
The output voltage droop due to a load transient is
dominated by the capacitance of the ceramic out-
put capacitor. During a step increase in load cur-
rent, the ceramic output capacitor alone supplies
the load current until the loop responds. Within two
or three switching cycles, the loop responds and
the inductor current increases to match the load
current demand. The relationship of the output volt-
age droop during the three switching cycles to the
output capacitance can be estimated by:
⎝
The term
appears in both the input
voltage ripple and input capacitor RMS current
equations and is a maximum when VO is twice VIN.
This is why the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT1146. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
3
·
VDROOP FS
ΔILOAD
COUT
=
·
The proper placement of the input capacitor (C2)
can be seen in the evaluation board layout in
Figure 2.
Once the average inductor current increases to the
DC load level, the output voltage recovers. The
above equation establishes a limit on the minimum
value for the output capacitor with respect to load
transients.
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low-ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance. This
problem often becomes apparent in the form of
excessive ringing in the output voltage during load
transients. Errors in the loop phase and gain meas-
urements can also result.
The internal voltage loop compensation also limits
the minimum output capacitor value to 4.7μF. This
is due to its effect on the loop crossover frequency
(bandwidth), phase margin, and gain margin.
Increased output capacitance will reduce the
crossover frequency with greater phase margin.
12
1146.2006.04.1.3
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
