AAT1143
1MHz 400mA Step-Down Converter
For the condition where the step-down converter is
in dropout at 100% duty cycle, the total device dis-
sipation reduces to:
Layout
The suggested PCB layout for the AAT1143 is
shown in Figures 2, 3, and 4. The following guide-
lines should be used to help ensure a proper layout.
PTOTAL = IO2 · RDSON(HS) + IQ · VIN
1. The input capacitor (C2) should connect as
closely as possible to VIN (Pin 3) and PGND
(Pins 6-8).
2. C1 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible.
Since RDS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
3. The feedback trace or OUT pin (Pin 2) should
be separate from any power trace and connect
as closely as possible to the load point.
Sensing along a high-current load trace will
degrade DC load regulation. If external feed-
back resistors are used, they should be placed
as closely as possible to the OUT pin (Pin 2) to
minimize the length of the high impedance
feedback trace.
4. The resistance of the trace from the load return
to the PGND (Pins 6-8) should be kept to a
minimum. This will help to minimize any error in
DC regulation due to differences in the poten-
tial of the internal signal ground and the power
ground.
Given the total losses, the maximum junction tem-
perature can be derived from the θJA for the
SC70JW-8 package which is 160°C/W.
For the condition where the buck converter is in
dropout at 100% duty cycle, the total device dissi-
pation reduces to:
PTOTAL = IO2 · RDSON(HS) + IQ · VIN
Since RDS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
Given the total losses, the maximum junction tem-
perature can be derived from the θJA for the
SC70JW-8 package which is 160°C/W.
TJ(MAX) = PTOTAL · ΘJA + TAMB
14
1143.2005.09.1.7
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