AAT1123
1MHz Step-Down Converter
Since RDS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
1. The input capacitor (C2) should connect as
closely as possible to VIN (Pin 3) and PGND
(Pins 6-8).
2. C1 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible.
3. The feedback trace or OUT pin (Pin 2) should
be separate from any power trace and connect
as closely as possible to the load point. Sensing
along a high-current load trace will degrade DC
load regulation. If external feedback resistors
are used, they should be placed as closely as
possible to the OUT pin (Pin 2) to minimize the
length of the high impedance feedback trace.
4. The resistance of the trace from the load return to
PGND (Pins 6-8) should be kept to a minimum.
This will help to minimize any error in DC regula-
tion due to differences in the potential of the inter-
nal signal ground and the power ground.
Given the total losses, the maximum junction tem-
perature can be derived from the θJA for the
SC70JW-8 package which is 160°C/W.
TJ(MAX)
=
PTOTAL
·
Θ
JA + TAMB
Layout
The suggested PCB layout for the AAT1123 is
shown in Figures 2, 3, and 4. The following guide-
lines should be used to help ensure a proper layout.
14
1123.2006.05.1.5
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
