AAT1106
600mA Step-Down Converter
closely as possible to the IC. This keeps the high fre-
quency content of the input current localized, mini-
mizing EMI and input voltage ripple. The proper
placement of the input capacitor (C1) can be seen in
the evaluation board layout in Figure 3. A laboratory
test set-up typically consists of two long wires run-
ning from the bench power supply to the evaluation
board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capac-
itor, can create a high Q network that may affect con-
verter performance. This problem often becomes
apparent in the form of excessive ringing in the out-
put voltage during load transients. Errors in the loop
phase and gain measurements can also result.
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the power
leads from the bench power supply, most applica-
tions do not exhibit this problem. In applications
where the input power source lead inductance can-
not be reduced to a level that does not affect the
converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with
the low ESR, ESL bypass ceramic. This dampens
the high Q network and stabilizes the system.
or three switching cycles, the loop responds and the
inductor current increases to match the load current
demand. The relationship of the output voltage
droop during the three switching cycles to the output
capacitance can be estimated by:
3 · ∆I
LOAD
C
=
OUT
V
· F
S
DROOP
Once the average inductor current increases to the
DC load level, the output voltage recovers. The
above equation establishes a limit on the minimum
value for the output capacitor with respect to load
transients. The internal voltage loop compensation
also limits the minimum output capacitor value to
4.7ꢀF. This is due to its effect on the loop crossover
frequency (bandwidth), phase margin, and gain
margin. Increased output capacitance will reduce
the crossover frequency with greater phase margin.
The maximum output capacitor RMS ripple current
is given by:
1
V
· (V
- V
)
OUT
IN(MAX)
OUT
I
=
·
RMS(MAX)
Output Capacitor Selection
L · F · V
2 · 3
IN(MAX)
The output capacitor is required to keep the output
voltage ripple small and to ensure regulation loop
stability. The output capacitor must have low
impedance at the switching frequency. Ceramic
capacitors with X5R or X7R dielectrics are recom-
mended due to their low ESR and high ripple cur-
rent. The output ripple VOUT is determined by:
Dissipation due to the RMS current in the ceramic
output capacitor ESR is typically minimal, resulting in
less than a few degrees rise in hot-spot temperature.
Thermal Calculations
There are three types of losses associated with the
AAT1106 step-down converter: switching losses,
conduction losses, and quiescent current losses.
Conduction losses are associated with the RDS(ON)
characteristics of the power output switching
devices. Switching losses are dominated by the gate
charge of the power output switching devices. At full
load, assuming continuous conduction mode(CCM),
a simplified form of the losses is given by:
V
OUT
· (V - V )
IN OUT
1
∆V
≤
· ESR +
OUT
V · f
IN
· L
8 · f
· C3
OSC
OSC
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7ꢀF
to 10ꢀF X5R or X7R ceramic capacitor typically pro-
vides sufficient bulk capacitance to stabilize the out-
put during large load transitions and has the ESR
and ESL characteristics necessary for low output
ripple. The output voltage droop due to a load tran-
sient is dominated by the capacitance of the ceram-
ic output capacitor. During a step increase in load
current, the ceramic output capacitor alone supplies
the load current until the loop responds. Within two
2
I
O
· (R
· V + R · [V - V ])
O DSON(LS) IN O
DSON(HS)
P
TOTAL
=
V
IN
+ (t · F · I + I ) · V
sw O Q IN
14
1106.2007.07.1.0
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