AWT6321
APPLICATION INFORMATION
Bias Modes
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
The power amplifier may be placed in either a Low Bias
mode or a High Bias mode by applying the appropriate
logic level (see Operating Ranges table) to the VMODE
voltages. The Bias Control table lists the recommended
modes of operation for various applications.
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE voltages.
Table 6: Bias Control
P
OUT
BIAS
MODE
APPLICATION
V
ENABLE
V
MODE
V
CC
V
BATT
LEVELS
< +16 dBm
> +16 dBm
CDMA - low power
Low
+2.4 V +2.4 V
+2.4 V 0 V
3.2 - 4.2 V
3.2 - 4.2 V
> 3.2 V
> 3.2 V
CDMA - high power
High
Optional lower VCC in low power
mode
< +7 dBm
Low
+2.4 V +2.4 V
1.5 V
> 3.2 V
> 3.2 V
Shutdown
-
Shutdown
0 V
0 V
3.2 - 4.2 V
GND at slug (pad)
VEN_CELL
1
14
13
12
11
10
9
GND
0.01 F
Bias Control
(1)
(2)
(2)
68 pF
TRL1
RFIN_CELL
2
TRL2
RFOUT_CELL
VMODE
VCC
3
4
1000 pF
(3)
VBATT
TRL5
2.2 F
10 F
5
GND
GND
N/C
(1)
(2)
RFIN_PCS
TRL3
6
7
Bias Control
(2)
15 pF
TRL4
RFOUT_PCS
VEN_PCS
8
0.01 F
GND
Note:
(1) Add blocking cap if DC voltage is present on input pin.
(2) TRL should be short and of 50 characteristic impedance.
(3) TRL 5 should be as long as possible (minimum of 0.1 at 800 MHz) and capable of handling 1200 mA current.
Figure 3: Application Circuit
Data Sheet - Rev 2.2
6
10/2008
ANADIGICS [ ANADIGICS, INC ]
