AWT6244
Tableꢀ4:ꢀElectricalꢀSpecificationsꢀ-ꢀTD-SCDMAꢀMode
(T
C
= +25 °C, VCC = +3.4 V, VBATT = +3.4 V, VENABLE = +2.4 V, 50 Ω system)
COMMENTS
PARAMETER
MIN
TYP
MAX
UNIT
P
OUT
V
MODE1
24.0
11.5
27
13.5
30.0
16.5
+27.5 dBm
+16 dBm
0 V
2.4 V
Gain
dB
dBc
dBc
%
-
-
-42
-42
-38
-38
+27.5 dBm
+16 dBm
0 V
2.4 V
ACLR1 at 1.6 MHz offset
ACLR2 at 3.2 MHz offset
-
-
-55
-55
-48
-48
+27.5 dBm
+16 dBm
0 V
2.4 V
Power-Added Efficiency
(without DC/DC Converter)
35
14
38
20
-
-
+27.5 dBm
+16 dBm
0 V
2.4 V
Quiescent Current (Icq)
Low Bias Mode
-
-
-
-
8
13
0.8
0.8
5
mA
mA
mA
mA
VMODE1 = +2.4 V
Mode Control Current
Enable Current
0.3
0.3
3.0
through VMODE pin, VMODE1 = +2.4 V
through VENABLE pin, VEN = +2.4 V
through VBATT pin, VMODE1 = +2.4 V
BATT Current
V
V
BATT = +4.3 V, VCC = +4.3 V,
ENABLE = 0 V, VMODE1 = 0 V
Leakage Current
Noise Figure
-
<1
5
µA
-
-
TBD
TBD
-
-
dB
dB
P
P
OUT < +27.5 dBm, VMODE = 0 V
OUT < 16 dBm, VMODE = +2.4 V
Harmonics
2fo
3fo, 4fo
-
-
-
-
-35
-35
P
OUT < +27.5 dBm
dBc
Input Impedance
-
-
-
2:1
VSWR
Load mismatch stress with no
permanent degradation or failure
8:1
-
VSWR Applies over full operating range
Data Sheet - Rev 2.0
4
05/2010
ANADIGICS [ ANADIGICS, INC ]
