ATA00501
Figure 11: Input Offset Voltage vs. Temperature
Indirect Measurement of Optical Overload
Optical overload can be defined as the maximum
optical power above which the BER (bit error rate)
increases beyond 1 error in 10 10 bits. The
ATA00501D1C is 100% tested at die sort by a DC
measurement which has excellent correlation with
an PRBS optical overload measurement. The
measurement consists of sinking a negative current
(see VOUT vs IIN figure) from the TIA and determining
the point of output voltage collapse. Also the input
node virtual ground during heavy AGC is checked to
verify that the linearity (i.e. pulse width distortion) of
the amplifier has not been compromised.
Measurement of Input Referred Noise Current
The Input Noise Current is directly related to
sensitivity . It can be defined as the output noise
voltage (Vout), with no input signal, (including a 30
MHz lowpass filter at the output of the TIA) divided by
the AC transresistance.
Figure 12: Input Referred Noise Spectral Density
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
Input Offset Voltage
V
DD
= 5.5 V
V
=
5.0V
DD
V
DD
=
4.5V
10
Temperature
o
C
60
- 40
CBY Connection
The C BY pad must be connected via a low
inductance path to a surface mount capacitor of at
least 56pF (additional capacitance can be added in
parallel with the 56 pF or 220 pF capacitors to
improve low frequency response and noise
performance). Referring to the equivalent circuit
diagram and the typical bonding diagram, it is critical
that the connection from CBY to the bypass capacitor
use two bond wires for low inductance, since any
high frequency impedance at this node will be fed
back to the open loop amplifier with a resulting loss
of transimpedance bandwidth. Two pads are
provided for this purpose.
Sensitivity and Bandwidth
In order to guarantee sensitivity and bandwidth
performance, the TIA is subjected to a
comprehensive series of tests at the die sort level
(100% testing at 25 oC) to verify the DC parametric
performance and the high frequency performance
(i.e. adequate |S21|) of the amplifier. Acceptably high
|S21| of the internal gain stages will ensure low
amplifier input capacitance and hence low input
referred noise current. Transimpedance sensitivity
and bandwidth are then guaranteed by design and
correlation with RF and DC die sort test results.
7
Hz
6
5
4
3
2
1
CT
R
f
50
pA/
C
T
=1.0pF
CT =0.5pF
1
10
100
1000
- 0.1
Frequency (MHz)
FIgure 13: Input Referred Noise vs Temperature
Input Referred Noise in (nA RMS)
Input Referred Noise Test Circuit
10
25dB
V
DD =
4.5 V
30
MHz
LPF
9
8
0.5pF
7
6
5
-40
0
TIA
V
DD
=5.5V
η(dBm)
= 10 LOG
6500
i
n
R
40
80
Temperature (
0
C)
61.
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
ANADIGICS [ ANADIGICS, INC ]
