ARA2008
LOGIC PROGRAMMING
Programming Instructions
The programming word is set through a 6 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
Table 7: Programming Word
D ATA B IT
Value
D
5
P5
D
4
P4
D
3
P3
D
2
P2
D
1
P1
D
0
P0
Table 8: Data Description
V AL U E
P5
P4
P3
P2
P1
P0
FU N C TION
(0 = on, 1 = by pass)
32 dB Attenuator Bi t
16 dB Attenuator Bi t
8 dB Attenuator Bi t
4 dB Attenuator Bi t
2 dB Attenuator Bi t
1 dB Attenuator Bi t
DATA
D
5
: MSB
D
4
D
3
D
2
D
1
D
0
: LSB
CLOCK
ENBL
Figure 4: Serial Data Input Timing
6
ADVANCED PRODUCT INFORMATION - Rev 0.0
10/2001
ANADIGICS [ ANADIGICS, INC ]
