AIT1042
Table 6: Digital 2-Wire Interface Specifications
(T
C
= +55 °C, VDD = +5.0 V, ref. Figure 3)
PARAMETER
CLK Frequency
Logic High Input (pins 23, 24)
Logic Low Input (pins 23, 24)
Logic Input Current Consumption (pins 23, 24)
Address Select Input Current Consumtion (pin 25)
Data Sink Current
(2)
Bus Free Time between a STOP and START
Condition
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW period of CLK
HIGH period of CLK
Set-up Time for a Repeated START Condition
Data Hold Time (for 2-wire bus devices)
Data Set-up Time
Rise Time of DATA and CLK signals
Fall Time of Data and CLK signals
Set-up Time for STOP Condition
Capacitive Load for Each Bus Line
SYMBOL
f
CLK
V
H
V
L
I
LOG
I
AS
I
AK
t
BUF
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
R
t
F
t
SU;STO
C
b
MIN
1
2.0
-
-
-
-
1.3
0.6
1.3
0.6
0.6
0.0
100
20 + 0.1C
b
(1)
20 + 0.1C
b
(1)
0.6
-
MAX
400
-
0.8
10
10
4.0
-
-
-
-
-
0.9
-
300
300
-
400
UNIT
kHz
V
V
A
A
mA
s
s
s
s
s
s
ns
ns
ns
s
pF
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum V
H
and maximum V
L
levels.
DATA
t
F
CLK
S
t
LOW
t
R
t
SU;DAT
t
F
t
HD;STA
t
SP
t
R
t
BUF
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
Figure 3: Serial 2-Wire Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.0
02/2009
Sr
t
SU;STO
P
S
6
ANADIGICS [ ANADIGICS, INC ]
