AS1545
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Characteristics
AV
DD
= DV
DD
= 2.7V to 5.25V, V
DRIVE
= 2.7V to AV
DD
/DV
DD
, internal/external reference = 2.5V, T
A
= -40 to +85°C
(unless otherwise specified).
Table 4. Timing Characteristics
Parameter
Master Clock Frequency
Conversion Time
1
Symbol
f
SCLK
t
CONVERT
Conditions
Min
1
Typ
Max
20
15 x
t
SCLK
750
Units
MHz
ns
t
SCLK
= 1/f
SCLK
f
SCLK
= 20 MHz
Quiet Time
CSN Fall to SCLK Fall Setup
Time
CSN Fall to D
OUT
Enable
SCLK Fall to D
OUT
Valid
2
t
QUIET
t
CSS
t
CSDOE
t
DOV
Minimum time between end of serial
read and next falling edge of CSN
V
IL
of CSN to V
IL
of SCLK
V
IL
of CSN to Corner of D
OUT
V
DD
= 2.7V
V
DD
= 5.25V
V
DD
= 2.7V
V
DD
= 5.25V
V
IL
to V
IL
of SCLK
V
IH
to V
IH
of SCLK
V
IH
of CSN to corner of D
OUT
to Tristate
V
IH
to V
IH
of CSN
V
IH
of SCLK to corner of D
OUT
to
Tristate
30
10
15
40
10
10
5
0.4
t
SCLK
0.4
t
SCLK
0.6
t
SCLK
0.6
t
SCLK
20
30
5
50
ns
ns
ns
ns
SCLK Fall to D
OUT
Hold
3
t
DOH
t
CL
t
CH
t
CSDOD
t
CSPW
t
DOD
ns
SCLK Low Pulse Width
SCLK High Pulse Width
CSN Rise to D
OUT
Disable
CSN Minimum Pulse Width
SCLK Fall to D
OUT
Disable
ns
ns
ns
1. Based on simulation and characterised samples.
2. V
IL
of SCLK to V
OH
of D
OUT
(rising edge) / V
OL
of D
OUT
(falling edge)
3. V
IL
of SCLK to V
OL
of D
OUT
(rising edge) / V
OH
of D
OUT
(falling edge)
Figure 3. Timing Diagram
CSN
t
CSPW
t
CSS
SCLK
1
t
CSDOE
DOUTA
0
0
DB11
0
DOUTB THREE-
STATE
3 LEADING ZEROES
2
3
4
t
DOV
DB10
DB9
DB2
DB1
DB0
t
CH
5
t
DOH
t
CL
14
t
CSDOD
t
QUIET
THREE-STATE
B
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