AS1543/44
Data Sheet - Detailed Description
Control Register
The AS1543/44 control register is a 13-bit, write-only register. Data is loaded into the register from pin DIN on the fall-
ing edge of the SCLK signal. Data is transferred on pin DIN at the same time as the conversion result is read from the
device. The data transferred on pin DIN corresponds to the AS1543/44 configuration for the next conversion. This
requires 16 serial clocks for every data transfer.
Only the information provided on the first 13 falling clock edges (after CSN falling edge) is loaded to the control regis-
ter. The control register bits are defined in Table 6.
Table 5. 12-Bit Control Register Format
0
12
(MSB)
11
10
9
8
7
6
5
4
3
2
1
(LSB)
WEAK/
TRIN
WRITE
SHADOW
CODING
SEQ
ADDR3 ADDR2 ADDR1 ADDR0
PM1
PM0
RANGE
SE/FDN
Table 6. Control Register Bit Definitions
Bit Number
Bit Name
Description
Determines if the subsequent 12 bits will be loaded to the control register.
1 = The subsequent 12 bits will be written to the control register.
0 = The subsequent 12 bits are not loaded to the control register and its
contents are unchanged.
WRITE
12
This bit is used in conjunction with the SHADOW bit to control the sequencer
(see Table 11 on page 17) and access the shadow register (see page 18).
SEQ
11
These four address bits and the bit SE/FDN are loaded at the end of the
present conversion sequence, and select which single analog input or pair of
input channels is to be converted in the next serial transfer. The selected input
channel is decoded as shown in Table 8 on page 15.
ADDR3:ADDR0
10:7
These bits also may select the final channel in a consecutive sequence as
described in Table 11 on page 17. The address bits corresponding to the
conversion result are also output on DOUT prior to the 12 bits of data (see
Serial Interface on page 20). The next channel to be converted on will be
selected by the multiplexer on the 14th SCLK falling edge.
These two power management bits set the mode of operation of the AS1543/
44 (see Table 10 on page 17).
PM1, PM0
SHADOW
6, 5
4
This bit is used in conjunction with the SEQ bit to control the sequencer (see
Table 11 on page 17) and access the shadow register (see page 18).
This bit selects the state of pin DOUT upon completion of the current serial
transfer.
1 = DOUT will be weakly driven to the channel address specified by bit
ADDR3 of the subsequent conversion.
WEAK/TRIN
3
0 = DOUT will return to tri-state at the end of the serial transfer (see Serial
Interface on page 20).
This bit selects the analog input range to be used for the subsequent
conversion.
This results in conjunction with bit SE/FDN in 4 possible analog input ranges,
as explained in Table 7 on page 15
RANGE
CODING
SE/FDN
2
1
0
This bit selects the type of output coding to be used for the conversion result.
1 = The output coding for the next conversion is straight binary.
0 = The output coding for the next conversion is twos complement.
This bit selects in conjunction with the adress bits ADDR3:ADDR0 the input
channels to be used (see Table 8 on page 15).
1 = 8/4 single-ended input channels
0 = 4/2 fully-differential channels
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