AS1538/AS1540
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics
Symbol
CMOS Digital I/O
V
IH
V
IL
V
OL
I
IH
I
IL
Input High Logic Level
Input Low Logic Level
Output Low Logic Level
Input High Leakage Current
Input Low Leakage Current
3mA sink current
V
IH
= +V
DD
V
IL
= GND
Straight binary
Specified performance
PD = 00 Full Power-Down
Analog Current in Static Mode,
3.6V
I
QSTAT
Analog Current in Static Mode,
5.25V
PD = 01 Internal Ref. OFF, ADC ON
PD = 10 Internal Ref. ON, ADC OFF
PD = 11 Internal Ref. ON, ADC ON
PD = 00 Full Power-Down
PD = 01 Internal Ref. OFF, ADC ON
PD = 10 Internal Ref. ON, ADC OFF
PD = 11 Internal Ref. ON, ADC ON
Quiescent Current at Full
Speed, 3.6V
I
Q
Quiescent Current at Full
Speed, 5.25V
PD = 01 Internal Ref. OFF, ADC ON
PD = 11 Internal Ref. ON, ADC ON
PD = 01 Internal Ref. OFF, ADC ON
PD = 11 Internal Ref. ON, ADC ON
2.7
0.04
400
500
800
0.04
450
550
850
500
850
650
915
5.25
1.2
500
600
900
1.5
550
650
950
600
950
800
1150
µA
µA
µA
µA
V
-1
+V
DD
x 0.7
-0.3
+V
DD
+ 0.5
+V
DD
x 0.3
0.4
1
V
V
V
µA
µA
Parameter
Condition
Min
Typ
Max
Unit
Data Format
Power Supply Requirements
+V
DD
Power Supply Voltage
1. Guaranteed by design and characterized on sample base.
2. THD measure out to 5th harmonic.
Timing Characteristics
+V
DD
=
+2.7
to 5.25V, T
AMB
= -40 to +85ºC (unless otherwise specified). All values referenced to V
IHMIN
and V
ILMAX
levels.
Table 4. Timing Characteristics
Symbol
f
SCL
t
BUF
T
HOLDSTART
t
LOW
t
HIGH
T
SETUPSTART
T
SETUPDATA
T
HOLDDATA
T
RISESCLK
1
Parameter
SCL Frequency
Bus Free Time Between
STOP and START Conditions
Hold Time for Repeated
START Condition
SCL Low Period
SCL High Period
Setup Time for Repeated
START Condition
Data Setup Time
Data Hold Time
SCL Rise Time
SCL Rise Time after
Repeated START Condition
and After an ACK Bit
Condition
Min
0.1
1.3
160
50
50
100
10
Typ
Max
3.4
Unit
MHz
µs
ns
75
75
ns
ns
ns
70
10
10
40
80
ns
ns
ns
ns
1
T
RISESCLK1
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