AS1538/AS1540
Data Sheet - Electrical Characteristics
Table 3. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
CMOS Digital I/O
+VDD
x 0.7
+VDD
+ 0.5
VIH
VIL
Input High Logic Level
Input Low Logic Level
V
V
+VDD
x 0.3
-0.3
VOL
IIH
Output Low Logic Level
Input High Leakage Current
Input Low Leakage Current
Data Format
3mA sink current
VIH = +VDD
0.4
1
V
µA
µA
IIL
VIL = GND
-1
Straight binary
Power Supply Requirements
+VDD
Power Supply Voltage
Specified performance
2.7
5.25
1.2
V
PD = 00 Full Power-Down
0.04
400
500
800
0.04
450
550
850
500
850
650
915
PD = 01 Internal Ref. OFF, ADC ON
PD = 10 Internal Ref. ON, ADC OFF
PD = 11 Internal Ref. ON, ADC ON
PD = 00 Full Power-Down
500
600
900
1.5
Analog Current in Static Mode,
3.6V
µA
IQSTAT
PD = 01 Internal Ref. OFF, ADC ON
PD = 10 Internal Ref. ON, ADC OFF
PD = 11 Internal Ref. ON, ADC ON
PD = 01 Internal Ref. OFF, ADC ON
PD = 11 Internal Ref. ON, ADC ON
PD = 01 Internal Ref. OFF, ADC ON
PD = 11 Internal Ref. ON, ADC ON
550
650
950
600
950
800
1150
Analog Current in Static Mode,
5.25V
µA
µA
µA
Quiescent Current at Full
Speed, 3.6V
IQ
Quiescent Current at Full
Speed, 5.25V
1. Guaranteed by design and characterized on sample base.
2. THD measure out to 5th harmonic.
Timing Characteristics
+VDD = +2.7 to 5.25V, TAMB = -40 to +85ºC (unless otherwise specified). All values referenced to VIHMIN and VILMAX
levels.
Table 4. Timing Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fSCL
SCL Frequency
0.1
3.4
MHz
Bus Free Time Between
tBUF
1.3
µs
ns
STOP and START Conditions
Hold Time for Repeated
START Condition
THOLDSTART
160
tLOW
tHIGH
SCL Low Period
SCL High Period
50
50
75
75
ns
ns
Setup Time for Repeated
START Condition
TSETUPSTART
100
10
ns
TSETUPDATA
THOLDDATA
Data Setup Time
Data Hold Time
ns
ns
70
40
1
SCL Rise Time
10
10
ns
TRISESCLK
SCL Rise Time after
Repeated START Condition
and After an ACK Bit
1
80
ns
TRISESCLK1
www.austriamicrosystems.com
Revision 1.03
5 - 20
AMSCO [ AMS(艾迈斯) ]
