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AS1538_1 参数 Datasheet PDF下载

AS1538_1图片预览
型号: AS1538_1
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4通道,12位I2C模拟数字转换器 [8/4-Channel, 12-Bit I2C Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 20 页 / 749 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1538/AS1540  
Data Sheet - Detailed Description  
Reference Voltage  
The AS1538/AS1540 can operate with an internal 2.5V reference or an external reference. If a +5V supply is used, an  
external +5V reference is required in order to provide full dynamic range for a 0V to +VDD analog input. The external  
reference can be as low as 1V. When using a +2.7V supply, the internal +2.5V reference will provide full dynamic range  
for a 0V to +2.5V analog input.  
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often  
referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This means that  
any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference volt-  
age is reduced.  
Digital Interface  
The AS1538/AS1540 supports the I2C serial bus and data transmission protocol in high-speed mode at 3.4MHz. The  
AS1538/AS1540 operates as a slave on the I2C bus. The bus must be controlled by a master device that generates the  
serial clock (SCL), controls the bus access, and generates the START and STOP conditions. Connections to the bus  
are made via the open-drain I/O pins SCL and SDA.  
Figure 24. Bus Protocol  
MSB  
SDA  
ACK from  
Receiver  
Slave Address  
R/W  
Direction Bit  
ACK from  
Receiver  
1
2
6
7
8
9
1
2
3-8  
8
9
SCL  
ACK  
ACK  
Repeat if More Bytes Transferred  
START  
STOP or  
Repeated  
START  
The bus protocol (as shown in Figure 24) is defined as:  
- Data transfer may be initiated only when the bus is not busy.  
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line  
while the clock line is HIGH will be interpreted as control signals.  
The bus conditions are defined as:  
- Bus Not Busy. Data and clock lines remain HIGH.  
- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a  
START condition.  
- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,  
defines the STOP condition.  
- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable  
for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.  
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data  
bytes transferred between START and STOP conditions is not limited and is determined by the master device.  
The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.  
Within the I2C bus specifications a high-speed mode (3.4MHz clock rate) is defined.  
- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the recep-  
tion of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge  
www.austriamicrosystems.com  
Revision 1.03  
11 - 20