AS1536/AS1537
Datasheet - Detailed Description
The devices’ input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize
high-speed transient events) and measure periodic signals with bandwidths exceeding the devices’ sampling rate.
Note: Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of
interest.
Input Protection
Internal protection diodes clamp the analog input to VDD and GND, allowing the input to swing from (GND - 0.3V) to
(VDD + 0.3V) without damage. However, for accurate conversions near full scale, the input must not exceed VDD by
more than 50mV, or be lower than GND by 50mV.
Note: If the analog input exceeds the supply by 50mV, limit the input current to 2mA.
Track/Hold
In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog
input at pin AIN charges capacitor CHOLD (see Figure 24 on page 12). Bringing CSN low ends the acquisition interval
and the charge on CHOLD represent the sampled input voltage.
In hold mode, the T/H switches are opened thus the input is disconnected from the capacitor CHOLD. During this mode
the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the
end of the conversion, the input side of the in meantime discharged CHOLD switches back to AIN, and CHOLD charges
to the input signal again.
The maximum time for the T/H to acquire a signal (tACQ) is a function of how quickly its input capacitance is charged.
tACQ increases proportionally to the input signal’s impedance, and at higher impedances more time must be allowed
between conversions. tACQ is also the minimum time needed for the signal to be acquired, and is calculated by:
tACQ = 10(RS + RIN) x 21pF
(EQ 1)
Where:
RIN = 4.5kΩ
RS = the input signal’s source impedance.
tACQ is never less than 1.5µs. Source impedances < 1kΩ do not significantly affect the AC performance of the devices.
Note: Higher source impedances can be used if a 0.01µF capacitor is connected to the analog input. Note that the
input capacitor forms an RC filter with the input source impedance, limiting the devices’ input signal bandwidth.
External Clock
The AS1536/AS1537 do not require an external clock for analog-to-digital data conversion. This allows the micropro-
cessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is
unrestricted if each clock phase is at least 200ns.
Note: The external clock must not be run while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures 25 - 27
(see page 14) for graphical timing and control information.
The falling edge on pin CSN initiates a conversion sequence:
1. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins.
2. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion.
3. The internal SAR stores the data during the conversion process.
4. Pin DOUT going high indicates the conversion process has completed.
5. The rising edge of pin DOUT can be used as a framing signal.
6. SCLK shifts the data out of this register any time after the conversion is complete.
7. DOUT transitions on the falling edge of pin SCLK.
8. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since
there are 12 data bits and one leading high-bit 13 falling clock edges are needed to shift out these bits, respectively.
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