AS1520/AS1521
Data Sheet - Detailed Description
Figure 23. Detailed Serial Interface Timing Waveforms
CSN
tCL
tCH
tCP
tCSW
tCSS
tCSO
SCLK
tDS
tDH
tDOH
tDOV
DIN
tDOD
tDOE
DOUT
tSTH
tSTE
tSTV
tSTD
SSTRB
The external serial clock shifts data in and out of the devices and drives the analog-to-digital conversion steps. Two
clock periods after the last bit of the control byte is written the output pin SSTRB pulses high for one clock period.
The serial data is shifted out at DOUT on each of the next 12 SCLK rising edges (see Figure 21 on page 17).
Pins SSTRB and DOUT go into a high-impedance state when CSN goes high. The conversion must complete in 120µs
or less, or consequently, droop on the sample-and-hold capacitors may degrade conversion results. Figure 23 shows
detailed serial-interface timing waveforms.
Transfer Functions
Output coding and transfer function depend on the control register bits MODE (page 15) and RANGE (page 15).
Figure 24. Straight Binary Transfer Function for
RANGE = 1 and MODE = 1
Figure 25. Straight Binary Transfer Function for
RANGE = 0 and MODE = 1
11...111
11...111
Full Scale (FS)
Full Scale (FS)
Transition
Transition
11...1110
11...1110
Full Scale = VREF
Zero Scale = 0
1LSB = VREF/1024
Full Scale = +VREF/2
Zero Scale = -VREF/2
1LSB = VREF/1024
11....101
11....101
00...011
00...010
00...001
00...000
00...011
00...010
00...001
00...000
0
1
2
3
FS - 3/2LSB
ZS ZS+1LSB
FS - 3/2LSB
Input Voltage AIN+ - AIN- (LSB)
Input Voltage AIN+ - AIN- (LSB)
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