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AS1521-BTST 参数 Datasheet PDF下载

AS1521-BTST图片预览
型号: AS1521-BTST
PDF下载: 下载PDF文件 查看货源
内容描述: 10位,单电源,低功耗, 400 /高达300ksps , 8通道A / D转换器 [10-Bit, Single-Supply, Low-Power, 400/300ksps, 8-Channel A/D Converters]
分类和应用: 转换器
文件页数/大小: 29 页 / 1047 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1520/AS1521  
Data Sheet - Pinout  
4 Pinout  
Pin Assignments  
Figure 2. Pin Assignments (Top View)  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
VDD3  
VDD1  
VDD2  
SCLK  
CSN  
3
4
5
DIN  
AS1520/  
AS1521  
6
SSTRB  
DOUT  
7
8
GND  
REFADJ  
9
10  
REF  
Pin Descriptions  
Table 1. Pin Descriptions  
Pin Number  
Pin Name  
CH0:CH7  
COM  
Description  
Analog Sampling Inputs. These eight pins serve as analog sampling inputs.  
Common Analog Inputs. Tie this pin to ground in single-ended mode.  
Positive Supply Voltage  
1:8  
9
10  
VDD3  
Reference-Buffer Output/A/DC Reference Input. This pin serves as the reference  
voltage for analog-to-digital conversions. In internal reference mode, the reference  
buffer provides a +2.50V nominal output, externally adjustable at pin REFADJ. In  
external reference mode, disable the internal buffer by pulling pin REFADJ to VDD1.  
11  
REF  
Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie this  
pin to VDD1.  
12  
13  
14  
REFADJ  
GND  
Analog and Digital Ground  
Serial Data Output. Data is clocked out at the rising edge of pin SCLK. DOUT is high  
impedance when CSN is high.  
DOUT  
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB is  
clocked out. SSTRB is high impedance when CSN is high.  
15  
16  
17  
SSTRB  
DIN  
Serial Data Input. Data is clocked in at the rising edge of SCLK.  
Active-Low Chip Select. Data will not be clocked into pin DIN unless CSN is low.  
When CSN is high, pins DOUT and SSTRB are high impedance.  
CSN  
Serial Clock Input. This pin clocks data into and out of the serial interface, and is used  
to set the conversion speed.  
18  
SCLK  
Note: The duty cycle must be between 40 and 60%.  
Positive Supply Voltage  
19  
20  
VDD2  
VDD1  
Positive Supply Voltage  
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