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AS1520-BTST 参数 Datasheet PDF下载

AS1520-BTST图片预览
型号: AS1520-BTST
PDF下载: 下载PDF文件 查看货源
内容描述: 10位,单电源,低功耗, 400 /高达300ksps , 8通道A / D转换器 [10-Bit, Single-Supply, Low-Power, 400/300ksps, 8-Channel A/D Converters]
分类和应用: 转换器
文件页数/大小: 29 页 / 1047 K
品牌: AMSCO [ AUSTRIAMICROSYSTEMS AG ]
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AS1520/AS1521
Data Sheet
- E l e c t r i c a l
Characteristics
Table 3. AS1520 Electrical Characteristics (Continued)
Parameter
Conditions
Capacitive Bypass at
C
BYPREF
ADJ
REFADJ
REFADJ Output Voltage
REFADJ Input Range
For small adjustments, from 1.22V
REFADJ Buffer Disable
To power down the internal reference
Threshold
Buffer Voltage Gain
External Reference:
Reference buffer disabled, reference applied to pin REF
REF Input Voltage Range
8
Symbol
Min
0.01
Typ
Max
10
Units
µF
V
mV
1.22
±100
1.4
2.045
V
DD1
+
50mV
200
350
320
5
0.7 x
V
DD
0.3 x
V
DD
0.2
V
DD1
-
1
V
V/V
1.0
V
REF
= 2.50V,
f
SCLK
= 6.4MHz
V
REF
= 2.50V, f
SCLK
= 0
Power-Down, f
SCLK
= 0
V
REF Input Current
Digital Inputs:
DIN, SCLK, CSN
V
INH
V
INL
Input High Voltage
Input Low Voltage
µA
V
V
V
µA
pF
V
V
µA
pF
V
HYST
Input Hysteresis
I
IN
Input Leakage
C
IN
Input Capacitance
Digital Outputs:
DOUT, SSTRB
V
OL
Output Voltage Low
V
OH
Output Voltage High
I
L
Tri-State Leakage Current
C
OUT
Tri-State Output Capacitance
Power Supply
V
DD1
,
9
V
DD2
,
Positive Supply Voltage
V
DD3
V
IN
= 0 or V
DD2
-1
5
+1
I
SINK
= 5mA
I
SOURCE
= 1mA
CSN = V
DD2
CSN = V
DD2
0.4
4
-10
5
+10
4.5
Normal Operation with
10
External Reference
Normal Operation with
10
Internal Reference
Reduced-Power Mode
Full Power-Down Mode
11
5.5
2.8
3.3
0.4
0.5
3.3
3.8
0.8
2
+2
V
I
VDD1
,
I
VDD2
,
I
VDD3
Supply Current
V
DD1
= V
DD2
=
V
DD3
= 5.5V
mA
µA
mV
PSR
Power-Supply Rejection
V
DD1
= V
DD2
= V
DD3
= 5V ±10%
-2
±0.1
1. Tested at V
DD1
= V
DD2
= V
DD3
= +5V, COM = GND, bit
= 1, single-ended input mode.
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to V
DD1
.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA
is a result of production test limitations.
8. AS1520/AS1521 performance is limited by the device noise floor, typically 300µVp-p.
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