AS1507
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1507 contains two resistor arrays with 255 resistive elements each (tap points), and has a total end-to-end
resistance of 10, 50, or 100kΩ
The device provides high, low, and wiper terminals for a standard voltage-divider configuration. Pins HIGH, LOW, and
WIPER can be connected in any configuration as long as their voltages fall between GND and V
DD
.
A 3-wire, SPI-compatible serial interface controls movement of the wiper among the 256 tap points. The EEPROM
stores the wiper position and recalls the stored wiper position upon power-up. The EEPROM typically holds wiper data
for 150 years and up to 10M wiper store cycles.
Analog Circuit
The 256 tap points are accessible to the wiper along the resistor string between pins HIGH and LOW (similar to the
end terminals of a mechanical potentiometer). The wiper tap point is selected by programming 8 data bits and a control
byte via the 3-wire serial interface
Note:
Integrated power-on reset circuitry loads the wiper position from the EEPROM at power-up.
Digital Interface
The AS1507 uses an SPI-compatible 3-wire interface for command settings of the device consisting of two input sig-
nals (chip-select - CSN, and data clock - SCLK) and one bi-directional data pin (SDIO). Driving CSN low enables serial
interface and the command/data are passed into the device synchronously by each SCLK rising edge.
There are 16-bit commands for write data into the wiper register or the non-volatile memory, and 8-bit commands for
transferring data between wiper register and non-volatile memory and to read the data stored in the wiper register or
non-volatile memory. The 8-bit commands can be implemented in 16-bit command structure alternatively. In this case
the first 8 bits shifted through the SPI interface are not significant. The data byte passed at writing commands repre-
sents the position of the wiper.
After loading the 8- or 16-bit command while CSN is low, the loaded command is executed at the next rising edge of
CSN, simultaneously the serial interface is disabled. The CSN signal must be low during the whole serial input stream
through the SPI, otherwise data on the SPI interface are corrupted.
Note:
If the data-in stream does not exactly contain 8 or 16 digits, no command is executed at the rising edge of
CSN.
Figure 20. Serial Data Timing
CSN
t
CS0
t
CSS
SCLK
t
CL
t
CH
...
t
CSW
t
CS1
t
CP
t
CSH
...
t
DS
t
DH
SDIO
...
Standby Mode
Low-power standby mode is enabled at CSN high. After a read access standby mode is entered 2 cycles of SCLK
after issuing the last bit of the data wiper or non-volatile register. If the digital inputs are stable V
DD
or GND there is only
leakage power dissipation of the device.
This power dissipation is defined with 0.1uA (typ) at 25ºC.
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