AS1500
Data Sheet
- Electrical Characteristics
Table 4. Electrical Characteristics – 50k and 100k Versions
Symbol
t
S
_50k
VW Settling Time
t
S
_100k
e
NWB
_50k
e
NWB
_100k
1.
2.
3.
4.
5.
6.
Resistor Noise Voltage
Parameter
Conditions
R
WB
= 50kΩ, V
A
= V
CC
, V
B
= 0V,
±1% Error Band
R
WB
= 100kΩ, V
A
= V
CC
, V
B
= 0V,
±1% Error Band
R
WB
= 50kΩ, f =1kHz
R
WB
= 100kΩ, f =1kHz
Min
Typ
9
18
20
29
1
Max
Units
µs
µs
nV/
√
Hz
nV/
√
Hz
Typicals represent average readings at 25ºC and V
CC
= 5V.
Wiper is not connected. I
AB
= 70µA for the 50kΩ version and 35µA for the 100kΩ version.
All Tempcos are guaranteed by design and not subject to production test.
Terminal A is not connected. I
W
= 70µA for the 50kΩ version and 35µA for the 100kΩ version.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance
tests are measured with 2.5V bias on the measured terminal. The remaining resistor terminals are left open cir-
cuit.
7. Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.
8. P
DISS
is calculated from (I
DD
×V
CC
). CMOS logic level inputs result in minimum power dissipation.
9. All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteris-
tics use V
CC
=5V.
AS150x – SPECIFICATIONS
V
CC
= 3V±10% or 5V±10%, V
A
= V
CC
, V
B
= 0V, –40ºC
≤
T
A
≤
+125ºC unless otherwise noted.
Table 5. Switching Characteristics
Symbol
Parameter
23
Conditions
Min
Typ
1
Max
Unit
Switching Characteristics
t
CH
, t
CL
t
DS
t
DH
t
CSS
t
CSWH
t
CSWL
t
CSH
t
CS1
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CSN Setup Time
CSN High Pulsewidth
CSN Low Pulsewidth
CK Fall to CSN Rise
Hold Time
CSN Rise to Clock Rise
Setup
Clock Level High or Low
50
5
5
10
10
100
0
10
ns
ns
ns
ns
ns
ms
ns
ns
1. Typicals represent average readings at 25ºC and V
CC
=5V.
2. Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with
2.5V bias on the measured terminal. The remaining resistor terminals are left open circuit.
3. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1ns
(10% to 90% of V
CC
) and timed from a voltage level of 1.6V. Switching characteristics are measured using
V
CC
=3V or 5V. To avoid false clocking, a minimum input logic slew rate of 1V/µs should be maintained.
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