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AS1367-BTDT-12 参数 Datasheet PDF下载

AS1367-BTDT-12图片预览
型号: AS1367-BTDT-12
PDF下载: 下载PDF文件 查看货源
内容描述: 150毫安,自适应低压差线性稳压器 [150mA, Adaptive Low Drop-Out Linear Regulator]
分类和应用: 稳压器
文件页数/大小: 14 页 / 1156 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1367  
Datasheet - Application Information  
9 Application Information  
Capacitor Selection and Regulator Stability  
Ceramic capacitors are highly recommended as they offer distinct advantages over their tantalum and aluminum  
electrolytic components. For stable operation with load currents up to the maximum over the entire device temperature  
range, use a 3.3µF (min) ceramic output capacitor with an ESR <0.2Ω. Use large output capacitor values (10µF max)  
to reduce noise and improve load transient-response, stability and power-supply rejection.  
Note: Some ceramic capacitors exhibit large capacitance and ESR variations with variations in temperature. Z5U  
and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10ºC. With X7R or X5R  
capacitors, a 3.3µF capacitor should be sufficient at all operating temperatures.  
Power Supply Rejection Ratio  
The AS1367 are designed to deliver low dropout voltages and low quiescent currents. Power-supply rejection is  
typically 60dB at 10kHz. To improve power supply-noise rejection and transient response, increase the values of the  
input and output bypass capacitors.  
The Electrical Characteristics on page 4 show also the device line- and load-transient responses. For further details  
see the Power-Supply Rejection Ratio vs. Frequency graph in the Figure 9 on page 7.  
Dropout Voltage  
For standard products with output voltage greater than the minimum VIN (1.2V), the minimum input-output voltage  
differential (dropout voltage) determines the lowest usable supply voltage. This determines the useful end-of-life  
battery voltage in battery-powered systems. The dropout voltage is a function of the P-MOSFET drain-to-source on-  
resistance multiplied by the load current, and it is calculated by:  
VDROPOUT = VIN VOUT = RDS(ON) × IOUT  
(EQ 3)  
Where:  
RDS(ON) is the drain-to-source on-resistance.  
IOUT is the output current.  
Figure 17. Application Diagrams  
External Voltage Level Detection  
(Input Monitoring)  
Internal Voltage Level Detection  
(Output Monitoring)  
Input  
2V to 5.5V  
Output  
1.2V to 5.0V  
Input  
2V to 5.5V  
Output  
1.2V to 5.0V  
OUT  
IN  
IN  
OUT  
C
C
IN  
OUT  
C
C
IN  
OUT  
AS1367  
R
1µF  
3.3µF  
PU  
AS1367  
R
1µF  
PU  
3.3µF  
100kΩ  
100kΩ  
IN  
POK  
IN  
POK  
C
10nF  
BYP  
C
10nF  
BYP  
ON /  
OFF  
ON /  
OFF  
BYP  
EN  
BYP  
EN  
GND  
SET  
R
ADJ  
GND  
SET  
270kΩ  
www.austriamicrosystems.com  
Revision 1.02  
11 - 14