AS1340
Datasheet - Detailed Description
8 Detailed Description
The AS1340 features a current limiting circuitry, a fixed-frequency PWM architecture, power-OK circuitry, thermal pro-
tection, and an automatic powersave mode in a tiny package, and maintains high efficiency at light loads.
Figure 27. AS1340 - Block Diagram with Shutdown Disconnect Switch
L1
4.7µH
3
SWVIN
6
SWOUT
4
POK
LX
5
VIN = 2.7V
to 5.5V
2
1.13V
–
+
VCC
VOUT
Good
VIN to 50V
CIN
1µF
PWM
Control
Sync Drive
Control
0.9Ω
1 MHz
R1
CFF*
Current
Sense
Spread
Spectrum
Ramp
Σ
Slope
Compensator
Generator
AS1340
+
–
–
COUT
8
PWM
Comp
–
FB
VC
gm Error
Amp
+
1
RC
CC
Shutdown
Control
Shutdown
CP2
EN
1.25V
Ref
Powersave
R2
Operation
Control
Powersave
GND
7,9
* Optional
Automatic powersave mode regulates the output and also reduces average current flow into the device, resulting in
high efficiency at light loads. When the output increases sufficiently, the powersave comparator output remains high,
resulting in continuous operation.
For each oscillator cycle, the power switch is enabled. A voltage proportional to switch current is added to a stabilizing
ramp and the resulting sum is delivered to the positive terminal of the PWM comparator.
The error amplifier compares the voltage at FB with the internal 1.25V reference and generates an error signal (VC).
When VC is below the powersave mode threshold voltage the automatic powersave-mode is activated and the hyster-
etic comparator disables the power circuitry, with only the low-power circuitry still active (total current consumption is
minimized).
When a load is applied, VFB decreases; VC increases and enables the power circuitry and the device starts switching.
In light loads, the output voltage (and the voltage at FB) will increase until the powersave comparator disables the
power circuitry, causing the output voltage to decrease again. This cycle is repeated resulting in low-frequency ripple at
the output.
The POK output indicates whether the output voltage is within 90% of the nominal output voltage level or not. When
EN is low, the circuit is not active and POK gives a high signal when connected to VCC by a pull-up resistor. When EN
goes high, POK goes low after appr. 50µs and will go high when the output reaches 90% of the nominal output voltage
(see Figure 20 on page 7). When input and output voltage are almost the same, it may happen that the POK Signal
does not go low because VOUT reaches 90% before the delay has expired. The open-drain POK output sinks current,
when EN is high and the output voltage is below 90% of the nominal output voltage.
Thermal protection circuitry shuts down the device when its temperature reaches 145ºC.
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