AS1334
Datasheet - Application Information
Layout Considerations
The AS1334 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an
inductorbased switching topology. During the first half of the switching cycle, the internal PMOS switch turns on, the
input voltage is applied to the inductor, and the current flows from PVDD line to the output capacitor (C2) through the
inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The inductor current
continues to flow via the inductor from the device PGND line to the output capacitor (C2). Referring to Figure 24, the
AS1334 has two major current loops where pulse and ripple current flow. The loop shown in the left hand side is most
important, because pulse current shown in Figure 24 flows in this path. The right hand side is next. The current
waveform in this path is triangular, as shown in Figure 24. Pulse current has many high-frequency components due to
fast di/dt. Triangular ripple current also has wide high-frequency components. Board layout and circuit pattern design
of these two loops are the key factors for reducing noise radiation and stable operation. Other lines, such as from
battery to C1(+) and C2(+) to load, are almost DC current, so it is not necessary to take so much care. Only pattern
width (current capability) and DCR drop considerations are needed.
Figure 24. Current Loop
VIN
3.25V to 5.5V
i
fOSC = 2MHz
i
+
VDD
C1
- 10 µF
PVIN
L1
3.3 µH
VOUT
SW
FB
EN
C2
+
-
10 µF
SGND
PGND
POK
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