欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS1324 参数 Datasheet PDF下载

AS1324图片预览
型号: AS1324
PDF下载: 下载PDF文件 查看货源
内容描述: 1.5MHz的, 600毫安, DC / DC降压型稳压器 [1.5MHz, 600mA, DC/DC Step-Down Regulator]
分类和应用: 稳压器
文件页数/大小: 20 页 / 910 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号AS1324的Datasheet PDF文件第4页浏览型号AS1324的Datasheet PDF文件第5页浏览型号AS1324的Datasheet PDF文件第6页浏览型号AS1324的Datasheet PDF文件第7页浏览型号AS1324的Datasheet PDF文件第9页浏览型号AS1324的Datasheet PDF文件第10页浏览型号AS1324的Datasheet PDF文件第11页浏览型号AS1324的Datasheet PDF文件第12页  
AS1324  
Data Sheet - Detailed Description  
8 Detailed Description  
The AS1324 is a high-efficiency buck converter that uses a constant-frequency current-mode architecture. The device  
contains two internal MOSFET switches and is available in adjustable- and fixed-output voltage versions.  
Figure 21. Block Diagram  
Ramp  
Compensator  
VIN  
4
ICOMP  
+
OSC  
VIN  
CIN  
10µF  
OSCN  
Frequency  
Shift  
5
AS1324  
VOUT/VFB  
0.6V  
+
Error  
R1  
Amp  
FB  
R2  
PMOS  
NMOS  
OVDET  
+
Digital  
Logic  
Anti-  
Shoot  
Through  
0.6V +  
ΔVOVL  
4.7µH  
VOUT  
3
+
SW  
COUT  
10µF  
1
0.6V  
Reference  
0.6V -  
ΔVOVL  
EN  
+
IRCMP  
Shutdown  
2
GND  
Not applicable to AS1324  
AS1324-12: R1 + R2 = 600kΩ  
AS1324-15: R1 + R2 = 750kΩ  
AS1324-18: R1 + R2 = 900kΩ  
Main Control Loop  
During PWM operation the converters use a 1.5MHz fixed-frequency, current-mode control scheme. Basis of the cur-  
rent-mode PWM controller is an open-loop, multiple input comparator that compares the error-amp voltage feedback  
signal against the sum of the amplified current-sense signal and the slope-compensation ramp. At the beginning of  
each clock cycle, the internal high-side PMOS turns on until the PWM comparator trips. During this time the current in  
the inductor ramps up, sourcing current to the output and storing energy in the inductor’s magnetic field. When the  
PMOS turns off, the internal low-side NMOS turns on. Now the inductor releases the stored energy while the current  
ramps down, still providing current to the output. The output capacitor stores charge when the inductor current  
exceeds the load and discharges when the inductor current is lower than the load. Under overload conditions, when  
the inductor current exceeds the current limit, the high-side PMOS is turned off and the low-side NMOS remains on  
until the next clock cycle.  
When the PMOS is off, the NMOS is turned on until the inductor current starts to reverse (as indicated by the current  
reversal comparator (IRCMP)), or the next clock cycle begins. The IRCMP detects the zero crossing.  
The peak inductor current (IPK) is controlled by the error amplifier. When IOUT increases, VFB decreases slightly relative  
to the internal 0.6V reference, causing the error amplifier’s output voltage to increase until the average inductor current  
matches the new load current.  
The over-voltage detection comparator (OVDET) guards against transient overshoots by turning the main switch off  
and keeping it off until the transient is removed.  
www.austriamicrosystems.com  
Revision 1.03  
8 - 20